Actel has announced that its free Libero Gold integrated design environment (IDE) now provides expanded device support for designs up to one million gates. Users need only download and install a small service pack, the Libero 7.0 IDE Service Pack 1 (SP1), to their existing Libero 7.0 IDE software to immediately start developing one million-gate designs using Actel's FPGAs.
This free support covers all Actel single-chip device families, including the company's ProASIC3 and ARM7-enabled ProASIC3 FPGA families, and its new mixed-signal FPGA, the Actel Fusion programmable system chip (PSC). For the latter, Libero 7.0 SP1 also provides enhanced SmartGen Fusion IP peripheral generation flows that streamline the configuration of analog System Builder Components. In addition, SP1 includes enhanced algorithms that improve the place-and-route efficiency and quality of results for Actel's high-performance, antifuse-based Axcelerator FPGAs.
The Libero IDE Gold software contains all the tools of Libero IDE Platinum, except Palace AE Physical Synthesis, and WaveFormer Lite Reactive Test Bench and VCD import. Libero IDE 7.0 SP1 is available as a free software download from Actel's website.
Enhanced graphics on STM32U3
Design Automation
ST has introduced a new program designed specifically for users working with its mainstream STM32 MCUs, including STM32C0, U0, WBA, and U3 series.
Read more...XJTAG launches two new Flash programmers ASIC Design Services
DSP, Micros & Memory
XJTAG has announced XJExpress and XJExpress-FPGA, a pair of Flash programmers perfect for development, debug and in-service applications.
Read more...Siemens unveils groundbreaking Tessent AnalogTest software ASIC Design Services
Design Automation
Siemens Digital Industries Software recently introduced Tessent AnalogTest software - an innovative solution that reduces pattern generation time for analogue circuit tests from months to days.
Read more...STM32Cube MCU package for STM32WBA
Design Automation
The STM32CubeWBA utility gathers in one single package all generic embedded software components required to develop an application on STM32WBA series microcontrollers.
Read more...Why LabVIEW is critical to South Africa’s automation future
Design Automation
[Sponsored] In a world increasingly defined by connected systems, edge intelligence, and accelerating automation, the ability to build scalable, responsive, and maintainable engineering applications has never been more essential, and at the heart of this evolution lies LabVIEW.
Read more...Advanced PMIC for high-performance AI applications ASIC Design Services
Power Electronics / Power Management
Microchip Technology has announced the MCP16701, a Power Management Integrated Circuit (PMIC) designed to meet the needs of high-performance MPU and FPGA designers.
Read more...Take analogue designs from idea to reality
Design Automation
Bringing your analogue design ideas to life is simple with Microchip’s Analog Development Tool Ecosystem, part of its extensive range of solutions for both analogue and digital engineers.
Read more...Accurate power estimation
Design Automation
AMD Power Design Manager 2025.1 is now available – with support for AMD Versal AI Edge and Prime Series Gen 2 SoCs and production support for AMD Spartan UltraScale+ devices.
Read more...AMD Vivado Design Suite 2025.1
Design Automation
AMD Vivado Design Suite 2025.1 is here, and now with support for AMD Spartan UltraScale+ and next-generation Versal devices.
While every effort has been made to ensure the accuracy of the information contained herein, the publisher and its agents cannot be held responsible for any errors contained, or any loss incurred as a result. Articles published do not necessarily reflect the views of the publishers. The editor reserves the right to alter or cut copy. Articles submitted are deemed to have been cleared for publication. Advertisements and company contact details are published as provided by the advertiser. Technews Publishing (Pty) Ltd cannot be held responsible for the accuracy or veracity of supplied material.
printer friendly version