Actel has released a new version of its Libero integrated design environment (IDE) with new features intended to increase the flexibility, efficiency and performance of designs based on the company's field-programmable gate arrays (FPGAs).
In this Libero IDE 7.2 release, enhanced SmartGen, SmartTime and SmartPower tools offer new capabilities for IP generation to support the Actel Fusion programmable system chip (PSC) offerings. It also offers advanced timing and power analysis functionalities for designers using the Actel Fusion, ProASIC3 and RTAX-S families.
'As more system engineers turn to FPGAs, the Libero IDE 7.2 allows these designers to leverage the capabilities of the Fusion platform whether they are coming from a SoC, mixed-signal, discrete or analog design environment', said Jake Chuang, a senior director at Actel.
For a large variety of commonly used IP functions, the SmartGen tool provides users with design automation functionality to import existing cores and create new ones for their Fusion-based designs. New features include a sample sequencer, a sample sequence configurator and a visual phase-locked loop (PLL) configurator. Further, the state management capability that audits module changes and dependencies can now pass this information directly to Libero, allowing the designer to update all dependent modules with one click. SmartGen now also supports the direct update of nonvolatile memory for analog system blocks, reducing or eliminating lengthy iterations through synthesis.
Actel's SmartTime feature provides static timing analysis capabilities based on industry standards, such as Synopsys Design Constraints (SDC), as well as new visual constraint dialogues, easing the transition from ASICs to mixed-signal FPGAs. Enhancements to Actel's SmartPower power analysis tool enables users to perform detailed power-consumption analysis, helping to conserve power, cut costs and improve design reliability.
Advanced STM32 debugging in VS Code
Design Automation
Once an STM32 project is running in VS Code, the IAR C-SPY Debug extension adds a professional-grade analysis layer that scales with project complexity.
Read more...Introducing STM32CubeMX2 Altron Arrow
Design Automation
STMicroelectronics has launched STM32CubeMX2, a new evolution of its popular configuration and code generation tool for STM32 microcontrollers.
Read more...Miniature xtal for critical timing ASIC Design Services
Telecoms, Datacoms, Wireless, IoT
Microchip’s EX-423 Evacuated Miniature Crystal Oscillator is a compact, low-power timing solution designed for applications that demand high stability, accuracy, and long-term reliability.
Read more...AI assistant for STM32 developers
Design Automation
The STMicroelectronics STM32 Sidekick is an AI-driven assistant fully integrated into the STM32 ecosystem designed to streamline embedded development using STM32 microcontrollers.
Read more...Next-gen robotic systems initiative EBV Electrolink
Design Automation
EBV Elektronik recently introduced MOVE – Driving Robotics Forward, a new initiative designed by EBV Elektronik‘s Embedded Solutions team to support the development of next-generation robotic systems.
Read more...Reliable isolation for modern networks ASIC Design Services
Computer/Embedded Technology
The Pro-Tek5 PTI Series delivers reinforced 5 kV Ethernet isolation for applications that demand robust protection, reliable signal integrity, and full IEEE802.3 performance.
Read more...Reference design for NB-IoT plus GNSS Altron Arrow
Design Automation
ST Microelectronics’ STDES-ST87M01IGN is a reference design for the ST87M01 NB-IoT + GNSS module, implemented on a 2-layer FR4 PCB (90 x 60 x 1,6 mm).
Read more...ARINC 429 line driver evaluation board ASIC Design Services
DSP, Micros & Memory
Holt Integrated Circuits have announced the release of the ADK-85104 Evaluation Board, a compact, ready-to-use platform designed to help engineers rapidly evaluate and characterise Holt’s HI-85104.
While every effort has been made to ensure the accuracy of the information contained herein, the publisher and its agents cannot be held responsible for any errors contained, or any loss incurred as a result. Articles published do not necessarily reflect the views of the publishers. The editor reserves the right to alter or cut copy. Articles submitted are deemed to have been cleared for publication. Advertisements and company contact details are published as provided by the advertiser. Technews Publishing (Pty) Ltd cannot be held responsible for the accuracy or veracity of supplied material.
printer friendly version