The communications world is rapidly transitioning from a circuit-switched global network to a packet-switched, Internet Protocol (IP)-based network.
Broadband deployment, 'triple-play' (voice/video/data) services, 3G wireless, and other communications services enabled by this IP convergence are creating exciting new opportunities for consumers, service providers and equipment makers.
Addressing convergence, compatibility and cost
While IP is the wave of the future, traditional circuit-switched network infrastructure - based on time division multiplexing (TDM) and asynchronous transfer mode (ATM) - will continue to operate during a transitional period of convergence that will extend well into the next decade. IP-based networks must seamlessly converge with this existing infrastructure, which will remain particularly important in the access areas of the network. Access equipment must therefore support a range of interfaces and protocols and offer high-performance interworking among them all.
System and software compatibility is another essential aspect of this convergence. Few OEMs can support development of (and few carriers want to buy) completely new 'whiteboard' systems that do not leverage the strengths and capabilities of existing software and hardware designs.
Everyone, from consumers and carriers to developers, is demanding more performance and functionality at lower costs. The cost per bit for access networks continues to drop dramatically, spurring deployment of broadband and associated services throughout the world. These cost pressures are ultimately passed down to the communications processors and other silicon components used in network access equipment.
A communications engine made for convergence
Freescale Semiconductor continues to drive progress and innovation in the transition to packet networks by delivering high-performance PowerQUICC communications processors with advanced features and capabilities optimised for IP convergence applications. An industry-leading PowerQUICC architecture is now celebrating 10 years in the marketplace.
The MPC8360E PowerQUICC II Pro family is designed specifically to address the convergence, compatibility and cost issues of the IP transition. Based on the e300 Power Architecture technology SoC platform, the MPC8360 family consists of the MPC8360E and the MPC8358E processors with QUICC Engine technology and integrated security engines.
QUICC Engine technology is an evolutionary leap forward for the communications processor module (CPM), a function block that is fundamental to the PowerQUICC architecture. In essence, QUICC Engine technology is a programmable system-on-chip (SoC) function block that accelerates communications protocols. It features two RISC engines instead of the CPM's one, delivers up to four times the throughput, scales up to 500 MHz in MPC8360E processors, and supports DDR memory and Gigabit Ethernet.
While previous generations of CPMs excelled at Layer 2 applications, QUICC Engine technology adds Layer 3 and above to perform tasks, such as interworking, forwarding, switching and parsing-features that are particularly important for convergence. It also provides integrated multiprotocol processing and interworking at rates of up to 1,2 Gbps, enhancing overall system performance by offloading the companion Power Architecture technology processing core.
In addition, QUICC Engine technology is software and micro code compatible with previous CPMs. This backward compatibility enables equipment manufacturers to leverage their existing code base, which helps to minimise development costs and speeds time to market.
Target applications for the MPC8360E family include IP DSLAMs, voice over IP (VoIP) systems, 3G wireless infrastructures, passive optical networking (PON) equipment, multiservice access nodes (MSAN), and small-to-medium enterprise (SME) routers.
The three application examples that follow illustrate how the MPC8360E PowerQUICC II Pro processor family can address convergence, compatibility, and cost issues in specific equipment designs.
DSLAM
According to the DSL Forum, asymmetric DSL (ADSL), the leading DSL technology, reached 78 million global subscribers by mid-2004 and is expected to reach 500 million subscribers by 2010. The upsurge in DSL subscribers is expected to drive further deployment of digital subscriber line access multiplexers (DSLAMs) in the network.
Subscriber traffic is handled by DSLAM line cards and then passed to an ATM or Ethernet uplink card. The ATM or Ethernet uplink card aggregates the traffic into a faster uplink stream and feeds it to an Internet service provider or company WAN using a broadband remote access server.
The DSLAM market is evolving to a decentralised architecture that requires more processing power near the user, on the DSLAM card. Successful designs offer high bandwidth, more ports per card, and lower costs per port. Bandwidth must be configurable across ATM, PPP, Ethernet and IP. Support for a range of protocols, in addition to ATM and IP, is mandatory. Voice traffic must be prioritised to meet quality of service (QoS) standards.
The MPC8360E processor with QUICC Engine technology enables simplified system designs for multiple DSLAM applications, including IP-DSLAMs, multitenant unit (MTU) 'pizza box' DSLAMs, and DSLAM line cards. Because of its high level of integration, the MPC8360E can reduce component count, board power consumption, and board real estate, resulting in lower system costs and high port density. In addition, MultiCast and broadcast support are key for enabling key enablers of triple play services, in particular video over IP. With applications such as video gaming, video on demand and IPTV, this capability is an important aspect for IP DSLAMs, and the MPC8360 processor supports these features.
3G Node B network interface card
While system cost and processing power are key considerations for 3G equipment makers, flexibility and field upgrade capabilities are also essential. 3G interface cards must support the convergence of ATM and IP by adapting to many different protocols. They must be able to handle increasing numbers of network interfaces and speeds and prioritise voice traffic to maintain acceptable QoS levels.
The MPC8360E PowerQUICC II Pro processor provides a single-chip solution for all of the processing, protocol and interworking functions required for a 3G Node B network interface card. This can make it a cost-effective alternative to high-speed ASICs or FPGAs, which can require costly development cycles.
Specifically, the QUICC Engine carries voice, data and video using ATM or IP over eight T1 /E1 TDM links bundled with terminated protocols between the Node Bs and the node controller. The QUICC Engine block has eight unified communications controllers (UCCs), each of which can be easily programmed to handle a given communications protocol. For example, one of the UCCs in the QUICC Engine can be used to support either a Gigabit Ethernet or ATM interface to a backplane in the Node B card.
Media gateway
Media gateways exemplify both the complexities and advantages of IP convergence. The convergence of voice traffic onto the data network can bring significant benefits to carriers and enterprises alike, including reduced costs and simplified network management. Media gateways and switches that integrate VoIP, traditional telephone networks and ATM networks make this convergence possible.
Media gateways typically convert and compress TDM voice circuits onto ATM networks using a variety of adaptation protocols, or onto packet-based networks using IP, frame relay, or extensions of both. Voice switches may use interworking between the protocols in ATM and IP networks.
Media gateway designs must accommodate large numbers of voice (or fax and modem) circuits per slot, support a variety of network interfaces and speeds, and adapt as protocol standards evolve and improve. Successful designs allow advanced features and functions to be added in the field through software upgrades.
The MPC8360E PowerQUICC II Pro processor enables network and service convergence by supporting programmable protocol termination, multiple hardware interfaces and powerful interworking features. It offers a single platform architecture for IP packet networks and ATM-oriented systems with interworking between them. For ATM or IP packet processing, it enables a cost-effective, single-chip solution with low component counts and low power consumption.
More information about QUICC Engine technology, etc, can be found at www.freescale.com/QUICCEngine
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