Lattice Semiconductor Corporation has released its LatticeECP2-50 and LatticeECP2-12 FPGA devices, produced on 90 nm Fujitsu CMOS technology utilising 300 mm wafers.
The devices employ a DDR2 SDRAM memory interface at 533 Mbps, which the company claims is the industry's fastest rate in a low-cost FPGA. The devices have been optimised to deliver the features and cost structure required by designers for high-volume system applications, including an optimised logic and routing fabric, pre-engineered 840 Mbps parallel I/O, pre-engineered DDR2 memory interfaces and full feature sysDSP Blocks.
The overall family consists of a total of six logic densities, ranging from 6K to 70K LUTs (lookup tables) available in six popular package configurations. The LatticeECP2 family also provides other value-added features not commonly available in low-cost FPGAs, including dual-boot and TransFR (transparent field reconfiguration) I/O support for easy field logic updates, as well as bit-stream encryption with on-chip non-volatile key storage for enhanced design security.
Design support for the LatticeECP2 devices is provided by the latest version of the ispLEVER tool suite, which provides designers with access, in one software package, to all Lattice digital devices and includes synthesis and simulation support. An extensive range of IP (intellectual property) cores, particularly suited for high volume applications, is available for these devices from both Lattice and its IP partners. Four evaluation boards are also available for LatticeECP2 devices.
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