Lattice Semiconductor has developed a low power XAUI/HiGig/HiGig+ to SPI4.2 programmable fabric interface chip (FIC) solution implemented in its LatticeSCM FPGAs.
The solution, which utilises the LatticeSCM device's System Packet Interface Level 4 Phase 2 (SPI4.2) hard IP capability, and includes Lattice's 10 Gigabit Ethernet media access controller (MAC) soft IP core and the XAUI/HiGig/HiGig+ to SPI4.2 bridge design, provides a high-performance interface between the SERDES-based XAUI standard, used in 10G Ethernet networks, and SPI4.2, a popular parallel bus interface used by network processor unit (NPU) devices. When implemented in a LatticeSCM-15E FPGA packaged in a 256 fine pitch ball grid array (fpBGA) package, the bridge solution requires only 17 mm x 17 mm on a printed circuit board while consuming only 2,5 W of power.
In support of the bridge functionality, the LatticeSCM devices include from 4- to 32-channels of high-speed SERDES capable of supporting data rates from 600 Mbps to 3,8 Gbps. The flexiPCS Physical Coding Sublayer block embedded in the devices supports an array of popular communications data protocols, including Gigabit Ethernet, Fibre Channel, 10 Gigabit Ethernet (XAUI), PCI Express, Serial RapidIO and SONET/SDH.
As noted above, the LatticeSCM family also includes fully compliant embedded SPI4.2 controllers implemented in Lattice's low power masked array for cost optimisation (MACO) structured ASIC technology. The combination of these features, along with the LatticeSCM device's high-speed FPGA fabric and PURESPEED I/O technology, provides a platform for a variety of Ethernet Service Card applications.
The LatticeSCM family, as well as the LatticeSC family, which does not support MACO functionality but is otherwise identical, provides five logic density points between 15K and 115K LUTs. Embedded memory capacity ranges from 1 to 7,8 Megabits of dual-port block RAM with general-purpose 2 Gbps PURESPEED I/O ranging from 139 to 942 I/O. Each device features 8 analog PLLs and 12 digital DLLs for optimum clock flexibility.
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