Lattice Semiconductor recently announced expanded support for its LatticeMico32 32-bit embedded RISC microprocessor, an open source, soft IP core optimised for Lattice field programmable gate arrays (FPGAs). Availability of this enhanced solution, including new development tool and peripheral IP support, coincides with the release of Lattice's ispLEVER version 7.0 design tool suite. Core optimisation for the new non-volatile LatticeXP2 FPGA family, said to be the industry's first 'true' 90 nm FPGA using on-chip Flash technology, is also now available.
The LatticeXP2 FPGA combines Flash and SRAM technology on a single 90 nm die, enabling unique capabilities such as 'instant-on' operation, encrypted design security and flashBAK block RAM back-up. The LatticeMico32 processor, in combination with the LatticeXP2 devices, provides these benefits to designers:
* Instant code execution - by taking advantage of the high-speed configuration of the LatticeXP2 devices (~1 ms), the microprocessor can begin code execution almost immediately upon device power-up.
* FlashBAK - the previous operating context, both logic configuration as well as RAM contents, is available to the microprocessor at power-up through use of the unique flashBAK feature found in the LatticeXP2 devices. This feature allows the microprocessor to store important information, such as error codes or performance conditions, into non-volatile memory before power down. At power-up the information is automatically reloaded into the microprocessor memory to resume operation.
* Security - security of design code (both microprocessor software and FPGA hardware) is inherently high because configuration data is stored in on-chip Flash memory. In addition, LatticeXP2 devices offer other security and protection features, such as 128-bit AES encrypted design bitstream support and a keyed 'Lock' feature that protects against accidental or unauthorised device programming.
Lattice's ispLEVER design tool suite version 7.0 has expanded support for software coding and debug with the addition of new tools to the integrated development environment (IDE):
* Code trace - a tool that allows a programmer to trace the execution of program source code for debug.
* Standard Make C and C++ projects - provide support for programmers to create Standard Make projects, in addition to the existing Managed Make, wizard-driven project creation process.
* Small C library - based on the Newlib C library source, Small C focuses on efficient compilation for embedded applications.
Several new and updated peripheral IP cores are available with the release of ispLEVER 7.0 for use with the LatticeMico32 processor. These user configurable designs include:
DDR2 SDRAM controller - double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) controller.
* Tri-speed MAC - Ethernet media access controller operates in Gigabit or Fast Ethernet (10/100 Mbps) modes.
* Single data rate (SDR) SDRAM controller - now available on the LatticeXP2 devices for use with the LatticeMico32 processor.
SPI Flash ROM - the serial peripheral interface (SPI) Flash memory controller provides an invisible interface between a LatticeMico32 microprocessor and an external, industry-standard SPI Flash chip.
These peripherals join a number of LatticeMico32 peripheral functions previously introduced, including Timer, UART, GPIO, DMA controller and other blocks.
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