Design Automation


Lattice releases ispLEVER version 7.1

28 May 2008 Design Automation

Lattice Semiconductor has announced the immediate availability of its ispLEVER 7.1 FPGA design tool suite. The new tool release delivers a number of new functional and performance-enhancing features, including what is said to be the industry's first dedicated FPGA simultaneous switching output (SSO) Analyser. The SSO Analyser enables FPGA designers to actively analyse and optimise I/O pin placement and output switching characteristics to minimise undesirable noise and ground bounce on a printed circuit board.

To enable designers to achieve higher levels of productivity, the ispLEVER 7.1 design tools also deliver up to 30% faster FPGA design compile times and now support multiprocessor powered design compilation to achieve the fastest timing closure.

An enhanced Power Calculator enables FPGA designers to analyse and optimise power requirements early in their design. The tool includes a user-friendly interface that enables power analysis at the block level and examination of 'what-if' scenarios by changing design environment variables.



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