Altera has announced the availability of Quartus II software version 9.0, the company’s CPLD, FPGA and HardCopy ASIC development environment. The 9.0 version includes full support for Altera’s portfolio of transceiver FPGAs and HardCopy ASICs.
New features include:
* New SSN analyser tool: Provides designer feedback on potential simultaneous switching noise (SSN) violations during pin assignments, enabling faster board design and improving signal integrity.
Enhanced SOPC builder: Quartus II software further extends productivity advantages with SOPC Builder’s data sheet generator for easier hand-off between hardware and software engineers. In addition, SOPC Builder’s enhanced GUI now offers easier visualisation of large systems.
* Metastability analysis: Provides tools to auto-recognise potential metastability circuit issues, and to automate reporting of mean-time-between-failure (MTBF) values as an integrated part of the TimeQuest static timing analysis tool.
* Pin planner enhancements: A new clock network view now available within the pin planner allows designers to better manage clock resources, improving productivity and maximising performance.
In conjunction with the Quartus II software version 9.0, Altera unveiled the ModelSim Altera Starter Edition. Replacing the ModelSim Altera Web Edition, this enhanced simulator delivers several improvements, including 50% faster simulation speeds, support for all Altera devices and operating system support for Linux and Windows Vista platforms. The ModelSim Altera Starter Edition is integrated into the Quartus II software subscription and is also available free of charge to Quartus II Web Edition customers.
For designers requiring a full-featured simulation environment, Altera now separately offers the ModelSim Altera Edition, which was previously available only through a full Quartus II software subscription. The ModelSim Altera Edition delivers 33% faster simulation speeds compared to the ModelSim Altera Starter Edition, with no restrictions on design size.
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