Lattice Semiconductor has announced Version 8.0 of its ispLEVER FPGA design tool suite, which includes many enhancements for the design of high-speed double data rate (DDR) interfaces for the LatticeECP3 FPGA family.
These enhancements include automatic interface code generation to increase design productivity and reduce coding errors, as well as enhanced timing analysis that provides more transparency to circuit timing details.
The IPexpress tool can now generate the HDL for the most appropriate generic DDR interface based on user requirements such as direction, speed and bus width. This HDL has been specifically designed and validated for high-performance, robust operation. For the ECP3 family, certain DDR interfaces can now be implemented with much higher pin layout flexibility.
Since an important part of robust DDR interface operation is a clean transfer between the I/O and fabric clock domains, the trace static timing analysis report has been enhanced to include a ‘Timing Rule Check’ section that specifically analyses these clock domain transfers. This is done automatically and does not require users to define additional timing constraints. The IPexpress tool can now also optionally generate the complete I/O-specific circuitry for proprietary DDR memory interfaces, allowing designers to focus solely on the controller logic of their DDR1 and DDR2 DRAM interfaces.
Continuous improvement and innovation in place and route algorithms enable ispLEVER 8.0 software to complete large, congested designs 30% faster than with the previous ispLEVER 7.2 SP2 release.
Lattice continues to enhance and expand support for the innovative open source 32-bit RISC LatticeMico32 ecosystem. The GNU compiler (GCC) has been upgraded to version 4.3.0, which enables higher system performance and more flexible code deployment options. The tri-speed MAC IP can now be interconnected into higher throughput configurations. The component library now includes a dual port on-chip memory to enable high-speed information passing between Wishbone bus masters, and an enhanced SPI Flash controller allows both read and write access.
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