DSP, Micros & Memory

First 80C51 to have linear address range expanded to 16 MB

9 May 2001 DSP, Micros & Memory

Philips Semiconductors has announced that it has broken the 64 KB barrier with the first 8-bit 80C51 to support up to 16 MB of on-chip linear addressable memory. The 87C51Mx2 microcontroller family is the first in a broad line of large on-chip memory microcontrollers based on the company's new 51MX core.

The 51MX combines a significant increase in on-chip program and data memory together with high-level C language performance enhancements. Full binary object code compatibility is maintained, allowing design engineers to re-use existing 80C51 program codes. The architecture also retains 80C51 bus compatibility to allow re-use of existing peripherals and application specific integrated circuits (ASICs).

"Philips Semiconductors' 51MX family represents the future for the 80C51 architecture," says Geoff Lees, Director of Marketing, Microcontroller Business Line, Philips Semiconductors. "The 51MX is a unique embedded memory solution that creates a roadmap to greater functionality and increased performance, eliminating the need for software paging and costly external code-banking hardware."

The 51MX is an accelerated 80C51 architecture that executes instructions at twice the rate of standard 80C51 devices. Its 23 bit linear address supports up to 16 MB of on-chip or off-chip program and data memory.

The program counter is extended to 23 bits, and the stack pointer to 16 bits. A new 23 bit extended data pointer, together with two 24 bit universal pointers using existing general purpose registers, creates a 16 MB linear address range optimised for C compilers.

The 87C51MC2 is now available with 96 KB of OTP (one-time programmable) memory and 3 KB of RAM and the 87C51MB2 with 64 KB of OTP and 2 KB of RAM. Both devices operate with supply voltages from 2,7 V to 5,5 V and run at up to 24 MHz (5 V) with a typical instruction cycle time of 250 ns. The 87C51Mx2 family includes an integrated PCA (programmable counter array), two full-duplex enhanced UARTS, an industry-standard serial peripheral interface and a configurable watchdog timer.


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