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Programmable low-power timing devices
28 April 2010, Analogue, Mixed Signal, LSI
IDT has added new members to its VersaClock family of timing devices. The VersaClock low power (LP) devices are programmable clock generators specifically designed to reduce power consumption and optimise board layout in battery-operated consumer applications. They reduce power usage during power down (20 μW) and sleep mode with 32 kHz clock active (200 μW). The five new VersaClock LP devices (5P49EE801, 5P49EE802, 5P49EE601, 5P49EE602 and 5P49EE502) all feature four internal PLLs, each individually programmable and able to generate four unique frequencies. The frequencies can be generated from a clock input, a single TCXO or fundamental mode crystal reference. The new devices can generate frequencies from 5 kHz to 120 MHz, and are compatible with many different output types — from single-ended LVCMOS to differential LVDS. |
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