In semiconductor device manufacturing processes, sufficient wafer thickness is important due to the high degree of automation involved.
Prior to assembly processes, the wafers are thinned to achieve improved thermal dissipation properties. While the thinned wafers have desired material properties, the thin silicon substrate and edge properties make the wafer susceptible to damage.
These wafers are, however, highly desirable for a wide array of applications such as micro-electromechanical system (MEMS) and radio frequency (RF) applications. The increasing range of applications is driving the need for chip miniaturisation. Examples of such applications include biomedical sensors including video endoscopes and diagnostic pills. Even more importantly perhaps, producing ultra-thin chips is a key enabler technology for future three-dimensional (3D) integrated circuits (ICs).
Researchers at the Institut für Mikroelektronik Stuttgart (IMS) have been involved in the research of Chipfilm, ultrathin chips capable of being as thin as 20 micrometres. Developing on a prototype demonstrated in 2006, Chipfilm has made significant developments, and is heading toward the commercialisation stage.
Unlike the traditional subtractive approach of using back-thinning methods, the thickness of Chipfilm is controlled by an additive process in which crystals are grown in cavities. The technology allows the fabrication of ultrathin chips capable of high minimum bending radius, simultaneously reducing yield impact caused by wafer edge chipping caused by wafer dicing processes. With prototypes out since 2006, IMS has also been involved in the development of process technologies for the product to be mass produced. To facilitate assembly processes, chips are trenched along the sides, leaving only small regions (called anchors) attached to the substrate. By using anchors, the chip dice are supported throughout the processes prior to the die attach step where anchors are broken when a die is being picked.
With a possibility of much thinner chips, coupled with improved mechanical properties, technologies such as Chipfilm will be certain to make an impact in next generation 3D ICs. Frost & Sullivan believes that the usage of 3D IC technology in future devices is inevitable, as developers face a bottleneck related to interconnect delay. By stacking multiple devices, interconnect delays could be reduced. The development of Chipfilm has attracted the likes of Borch (2008), and the completion of basic level research including characterisation was successful in 2009.
The shift of ICs to 3D form would appear inevitable, with key research institutions and industry players investing aggressively on the technology. Frost & Sullivan expects chip stacking to play an important role in increasing the number of transistors in a device, in an economical manner. Emphasis on its development is evident from the milestones laid on the industry roadmap, ITRS. As critical as the process scaling done on silicon chips, minimal die thickness will be required in 3D IC to maximise transistor density. However, the lack of supporting technologies such as electronic design automation might hinder rapid deployment of 3D ICs. As such, the technology can be predicted to impact the semiconductor industry from 2014.
For more information contact Patrick Cairns, Frost & Sullivan, +27 (0)18 464 2402, [email protected], www.frost.com
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