Pentek’s Model 5341 is a software radio transceiver suitable for connection to HF or IF ports of a communications system. It features two A/D and two D/A converters, and is capable of bandwidths to 50 MHz and above. The board features built-in support for PCI Express Gen. 2 over the 3U VPX backplane and a fabric-transparent crossbar switch configuration adds Gigabit serial data paths for Xilinx Aurora or Serial RapidIO applications.
The device’s front end accepts two full-scale analog HF or IF inputs on front panel MMCX connectors at +10 dBm into 50 Ω with transformer coupling into 14-bit, 125 MHz A/Ds. The digital outputs are delivered into the Virtex-II Pro FPGA for signal processing or for routing to other module resources.
The 5341 features a GC4016 quad digital down-converter, accepting either four 14-bit inputs or three 16-bit digital inputs from the FPGA, which determines the source of GC4016 input data. These sources include the A/Ds, FPGA signal processing engine, SDRAM delay memory and data sources on the VPX backplane. Each GC4016 channel may be set for independent tuning frequency and bandwidth. For an A/D sample clock frequency of 100 MHz, the output bandwidth for each channel ranges from 5 kHz up to 2,5 MHz. By combining channels, output bandwidth of up to 5 or 10 MHz can be achieved.
A DAC5686 digital up-converter and dual D/A is attached to the FPGA, accepting baseband real or complex data streams with signal bandwidths up to 40 MHz. When operating as an up-converter, it interpolates and translates real or complex baseband input signals to any IF centre frequency between DC and 160 MHz. It delivers real or quadrature (I+Q) analog outputs through two 320 MHz 16-bit D/A converters to two front panel MMCX connectors at +4 dBm into 50 Ω. If translation is disabled, the DAC5686 acts as a two-channel interpolating 16-bit D/A with output sampling rates up to 500 MHz.
A Xilinx XC2VP50 Virtex-II Pro FPGA serves as a control and status engine with data and programming interfaces to each of the onboard resources including the A/D converters, digital down-converter, digital up-converter and D/A converters. Factory installed FPGA functions include data multiplexing, channel selection, data packing, gating, triggering and SDRAM memory control. An option provides general purpose I/O to VPX-P2 with 16 pairs of LVDS connections to the FPGA. Another option adds four full duplex 4x gigabit serial paths to the VPX-P1 connector.
Two independent internal timing buses can provide either a single clock or two different clock rates for the corresponding input and output signals. Each timing bus includes a clock, sync and gate or trigger signal. Signals from either timing bus can be selected as the timing source for the A/Ds, down-converter, up-converter and D/As. Two external reference clocks or two internal clocks may be used for each timing bus.
A front panel, 26-pin LVDS clock/sync connector allows multiple boards to be synchronised. In slave mode, each accepts differential LVDS inputs that drive the clock, sync and gate signals for the two internal timing buses. In master mode, the LVDS bus can drive one or both sets of timing signals from the two internal timing buses for synchronising multiple boards. Up to seven slave boards can be driven from the LVDS bus master, supporting synchronous sampling and sync functions across all connected boards.
Three independent banks of SDRAM are available to the FPGA (up to 1 GB). Built-in memory functions include an A/D data transient capture mode with pre- and post-triggering; a D/A waveform generator mode; and an A/D data delay mode for applications such as tracking receivers. The SDRAMs are also available as a resource for the two PowerPC processor cores within the FPGA. A 16 MB Flash memory supports booting and program store for these processors.
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