Texas Instruments has introduced three separate clock buffer families that offer elevated clock signal quality with very low additive jitter: the CDCLVC11xx, CDCLVD12xx/21xx and CDCLVP12xx/21xx families.
These buffers are targeted at a variety of communication applications with frequency support of up to 2 GHz (LVPECL), 800 MHz (LVDS) and 250 MHz (LVCMOS). They also save board space with small-footprint QFN and TSSOP options. In addition to supporting customer’s general-purpose clock buffering and distribution needs, these devices also meet stringent additive jitter requirements for wireless infrastructure, data communications and telecommunications, medical imaging and industrial applications.
The CDCLVC11xx clock buffer family for LVCMOS output generate 2, 3, 4, 6, 8, 10 and 12 copies of LVCMOS clock outputs from a single LVCMOS input. The devices boast additive jitter of less than 100 fs RMS (12 kHz–20 MHz) and output skew of 50 ps, maximum, to provide timing control among all outputs. Package modularity improves flexibility for various output configurations and simplifies board layout for multiple output requirements.
The CDCLVD12xx/21xx family for LVDS output generates 4, 8, 12 or 16 copies of LVDS clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs. They feature additive jitter of less than 300 fs RMS (10 kHz–20 MHz) and output skew of 20 ps, maximum (within same bank). Universal input support eliminates the need for additional external discretes for signal level translation.
Finally, the CDCLVP12xx/21xx clock buffer family, for LVPECL output, generates 4, 8, 12 or 16 copies of LVPECL clock outputs from one of two selectable LVCMOS, LVDS or LVPECL inputs. Their additive jitter is less than 100 fs RMS (10 kHz–20 MHz) and output skew is 15/20/25/30 ps maximum.
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