In the rapidly growing world of wireless telecommunications, numerous trends are gaining widespread popularity. Most dominant are wideband cellular radio transceivers that can support multiple carriers and multiple standards while preserving high signal quality required by bandwidth-efficient, complex modulation schemes. Design engineers envision a common hardware platform capable of processing a wide range of carriers, while supporting dynamic switching between transmission standards.
A PLL+VCO source which can be tuned over a wide frequency range is a critical circuit for the wideband transceiver. Generating local oscillator (LO) signals for the up- and down-conversion of RF signals is the primary application. The challenge is for a wideband PLL+VCO to cover a broad frequency range while maintaining excellent noise and low spurious performance at each frequency.
To meet these challenges, Hittite Microwave has introduced the HMC830LP6GE, a low-noise, wideband, fractional-N phase locked loop (PLL) with integrated voltage controlled oscillator (VCO). The device generates continuous frequencies from 25 MHz to 3 GHz and is targeted at LO frequency applications and generation of a very low-jitter ADC clock.
In addition to frequency coverage, key performance parameters to be considered when selecting a PLL+VCO are phase noise, spurious products and lock time.
Low phase noise is important in transmitter design as the local oscillator noise is amplified by the subsequent amplifier stages and eventually fed to the antenna together with the desired signal. The desired signal is accompanied by broadband noise originating from local oscillator phase noise. Noise generated can mask nearby lower-power stations or affect the receiver in a frequency division duplexing (FDD) system. Conversely, a low phase noise LO will give the designer greater margin for non-linearity and any other RF impairments in the transmitted signal. In general, low phase noise helps preserve transmitted signal quality.
Spurious products on the transmitted signal must also be kept at a low level so that they do not interfere with other users in the same system, or with nearby systems. On the receive side, low phase noise is crucial to obtaining good receiver signal-to-noise-ratio (SNR), especially at high signal levels when phase noise exceeds the thermal noise floor of the receiver.
Sometimes, the desired received signal will be accompanied by a large interferer in an adjacent channel. When the two signals are mixed with the LO output, the down-converted band consists of two overlapping spectra, with the desired signal suffering from significant noise due to the tail of the interferer. This effect is known as reciprocal mixing.
A spurious product at the channel spacing needs to be low because it will mix with the strong interferer and fold onto the desired signal. A high level of spurs can also affect lock time by forcing the design engineer to choose a narrower PLL loop bandwidth in order to provide sufficient attenuation of these spurs, but narrower loop bandwidth has the effect of slowing down the PLL response.
The HMC830LP6GE features enhanced phase noise and spurious performance across all frequencies, making it suitable for applications that require elevated signal quality performance and high SNR. It also features an integrated phase detector (PD) and delta-sigma modulator which are capable of operating up to 100 MHz in fractional mode to permit wider loop bandwidths with excellent spectral performance.
Other features present in the HMC830LP6GE include: exact frequency mode which enables users to generate frequencies with 0 Hz frequency error with minimal spurious emissions at multiples of channel spacing; CSP (cycle slip protection) technology that allows faster frequency convergence; and auto calibration of the VCO subsystem, which ensures single point calibration for optimal operation over the device‘s full temperature range.
Its performance characteristics make the device particularly suited for wideband multicarrier, multistandard cellular base stations as it can be used not only in up- or down-conversion, but also as a low-jitter clock LO generator, or even as a tuneable reference source for spurious-free performance. It is also targeted at high QAM microwave point-to-point links and communications test equipment.
The synthesiser’s figure of merit is -230/-227 dBc/Hz in integer and fractional modes respectively. Double sideband RMS jitter is less than 180 fs and noise floor is -171 dBc/Hz in fundamental mode at 2 GHz. The worst integer boundary spurious product is around -55 dBc when falling in-band. The device is housed in a 6 x 6 mm plastic leadless surface mount package and is stable over the -40°C to +85°C temperature range.
For more information contact Andrew Hutton, RF Design, +27 (0)21 555 8400, [email protected], www.rfdesign.co.za
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| Email: | [email protected] |
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