Infineon Technologies has introduced the next generation of its TriCore Unified Processor core architecture, one of the company's principal platforms for the design of System-on-Chip (SoC) integrated circuits for intelligent electronic devices. The TriCore 2 core implements design enhancements to improve overall system performance, while maintaining code compatibility with existing designs based on previous versions of the TriCore architecture.
According to the company, the principal enhancement to the core architecture is a new six-stage superscalar processor pipeline, which supports clock rates of 600 MHz in SoC devices manufactured in 0,13 µm process technology. The expected processing performance of the Tricore 2 core is 900 MIPS when operating at 600 MHz. When implemented in Infineon's 0,13 µm technology, the core will occupy approximately 2 mm2. A system implementation, including the core, memory management unit, 192 KB memory, and interfaces for coprocessor and external devices, will occupy less than 7 mm2.
See www.infineon.com or contact local distributor for Infineon Technologies, Electrocomp, (011) 458 9000.
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