Mentor Graphics recently announced the newest release of its HyperLynx product for high-speed design and analysis. Key features in the new release include advanced 3D channel and trace modelling, improved DDR signoff verification and accelerated simulation performance – up to 5X faster.
Engineers and designers who use the HyperLynx products during the system design process can quickly analyse potential high-speed design issues that can impact signal integrity, power integrity and electromagnetic interference (EMI) performance. These new capabilities can improve product quality and performance by correcting problems earlier in the design process.
Eric Bogatin, signal integrity evangelist at Bogatin Enterprises, a wholly owned subsidiary of Teledyne-LeCroy, provides the following testimonial: “In applications above 10 Gbps, insertion loss will often exceed -12 dB at the Nyquist and eyes will be completely closed. Successful designs require getting everything in the design right and building confidence in the design early in the design cycle with accurate simulations.
“The accuracy of the latest release of Mentor Graphics HyperLynx was recently validated with a 12,5 Gbps backplane design from Molex that included causal material models, copper surface texture contributions, via models, mode conversion and reflections from integrated S-parameter models of connectors.”
The new HyperLynx release decreases the amount of channel modelling that requires 3D analysis with advanced area fill-aware 2.5D planar trace extraction. When this advanced feature is enabled, the system will model variations in signal trace impedance or delays due to non-ideal planes and references (complex area fills with voids and cuts). The resulting impedance variation effects are included during time domain simulation and S-parameter model extraction.
Where necessary, HyperLynx also provides full 3D extraction and modelling. The designer can quickly select board areas for 3D full wave analysis, including exporting the full channel to the schematic editor for auto-port creation, assignment and simulation, tightly integrating the HyperLynx 3D EM full wave solver.
The newest release provides fast and powerful analysis results, with an average of 5x simulation performance improvement over the previous version. Internal tests of earlier versions and the new HyperLynx product release show a significant increase in the performance of the circuit simulator, especially for large-scale batch-mode analysis with complex stimulus (for example, DDRx simulation).
In addition to substantially increased performance, the upgraded simulator takes extra care to avoid accuracy problems for circuits involving short transmission lines, which are common when modelling PCB-trace meanders. Many competing simulators – especially SPICE-based ones – round up or eliminate the short delays of small routing segments based on the analysis time step, but the HyperLynx tool accurately preserves such effects, including during complex crosstalk simulations.
Mentor also recently added a design rule checking (DRC) product to Hyprelynx which efficiently performs best practice design rule checking on printed circuit board (PCB) layout databases. Driven by customisable rules, it can be executed by engineers and designers during the PCB layout process to quickly highlight potential high-speed design issues pertaining to signal integrity, power integrity and electromagnetic interference (EMI), without running detailed, time-consuming analysis.
The new HyperLynx DRC product comes with a standard set of coded rules targeted at PCB layout practices that have the potential to cause issues common in high-speed design. These standard rules are parametrically driven so users can customise them to meet specific best practices of their company. Samples of such issues include the following:
* Electromagnetic interference (EMI): Traces crossing plane splits, reference plane changes, nets near board edges, coupling to I/O net.
* Signal integrity (SI): Long interconnects, termination checks, impedance variations, crosstalk coupling.
* Power distribution network: Power net width, decoupling cap proximity.
The DRC tool is designed to allow customers to create their own best-practice rules using VBScript and/or Javascript. This gives electronics companies the opportunity to implement their intellectual property into the design process in an automated fashion.
HyperLynx DRC is interfaced with all major PCB layout tools including Mentor’s Expedition Enterprise, Board Station and PADS, Cadence Allegro and Zuken CR.
Mentor Graphics Announces New HyperLynx Technology with Advanced 3D Channel and Trace Modeling, Superior Accuracy and Fastest Simulation Performance.
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