Innoveda has unveiled a more powerful version of Regent, its wizard-like design and documentation tool for programmable register modules in embedded systems. Version 3.0 optimises the design process and implementation using a distributed model approach in which multiple register blocks are captured within one register table. Regent is an advanced tool designed specifically to handle the programming of system-on-chip (SoC) and embedded system registers. It provides a consistently synchronised flow to the various groups designing and testing HW/SW interface register blocks.
This approach frees firmware designers at companies such as Core Optics from the tedious and error-prone job of manually adapting software drivers to the latest hardware changes. Core Optics develops and manufactures optical networking solutions for the next-generation backbone transmission systems in the DWDM, SONET/SDH, ATM and IP areas. Through its subsidiary based in Nürnberg, Germany, Core Optics owns a world-class R&D operation. According to Christoph Schulien, CEO of Core Optics, "Regent enables us to design and document the HW/SW interface modules of our advanced ASICs, capturing large numbers of registers with their attributes in an intuitive way, and being able to automatically generate their RTL representation and SW macros. We have found Regent an important component in the design flow. It greatly supports our efforts to provide a collaborative environment for our hardware and software groups."
Distributed model
Commenting on the new distributed model approach in Version 3, Rami Rachamim, Director of Marketing for Innoveda's System-Level Design group, said, "This approach enables designers to capture in one register table multiple functionally related, yet autonomous, programmable register blocks and distribute them anywhere in their system." With its 'always-in-sync' software macros, which are used in software drivers to reflect the latest changes in registers, Regent provides a comprehensive solution for the fast-growing area of hardware/software interface design and verification. "Using programmable registers to configure hardware devices is not new, " Rachamim added. "Recently, however, software-controlled hardware configurations have become a key way to shorten overall hardware design cycles in systems. As a result, more and more programmable registers are required, and that is where Regent comes into play."
Regent adds design and documentation to systems and RTL methodology by generating synthesizable RTL from a structured register table. It also automatically generates software macros that depict hardware register addresses, size and bit position, eliminating errors that can occur in a manual approach. Designers simply include the latest C header file automatically generated by Regent. Regent Version 3.0 supports all Windows-based platforms in addition to Solaris and HP-UX.
For further information contact Kobus van Rooyen, ASIC Design Services, (011) 315 8316, [email protected]
| Tel: | +27 11 315 8316 |
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