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New class of DSP for telecoms is first to process 8, 16, 32, bit and floating-point data on single chip
16 Feb 2000, Analogue, Mixed Signal, LSI

Analog Devices has introduced the first DSP to use the com-pany's newest digital signal processor (DSP) architecture, dubbed TigerSHARC. The ADSP-TS001 TigerSHARC DSP is targeting telecommunications infrastructure equip- ment with a new level of integration and the unique ability to process 8, 16, 32 bit and floating-point data types on a single chip.

Each of these data types is critical to the next generation of telecommunications protocols currently under development says ADI, including IMT-2000 (also known as 3G wireless) and xDSL (digital subscriber line). Unlike any other DSP, the ADSP-TS001 has the unique ability to accelerate processing speed based on the data type. The chip also delivers the highest performance floating-point processing in the market according to the company.

In telecommunications infrastructure equipment, voice coder and channel coder protocols are developed around 16 bit data types. To improve signal quality, many telecoms applications employ line equalisation and echo cancellation techniques that boost overall signal quality and system performance. These algorithms benefit from the added precision of 32 bit and floating-point data processing, says Analog Devices. Also, adds the company, 8 bit native support is well-suited to the commonly used Viterbi channel decoder algorithm, as well as image processing where it is more straightforward and cost-effective to represent the red, green and blue components of the signal with 8 bit data types.

Breakthrough in DSP integration

Said to be the industry's most highly integrated DSP, on one chip, ADI has integrated 6 Mb of SRAM (static random access memory), fixed-and floating-point cores, four bi-directional link ports, a 64 bit external port, 14 DMA (direct memory access) channels and 128 registers in the TS001. This TigerSHARC DSP integrates 50% more on-chip memory than previously available solutions from ADI. For large-scale applications that require clusters of DSPs, ADI has integrated its patented link port technology, enabling direct chip-to-chip connections without the need for complex external circuitry.

Memory and I/O integration are carefully chosen to enable maximum data flow to and from the very high-speed core computational blocks. The DSP offers high-bandwidth internal memory access with the equivalent of 38400 T1 lines or more than 900 000 simultaneous phone calls moved in one second. This extremely high throughput assures a steady flow of data to and from the core - enabling the high sustained performance other processors lack.

TigerSHARC architectural advantages

According to the manufacturer, TigerSHARC employs a 'Static superscalar' architecture that can execute more multiply-accumulates (MAC) in a single cycle than any other DSP architecture. A MAC is a funda- mental instruction required for signal processing and is commonly used to measure true performance in realtime applications.

The ADSP-TS001 processes 1,2 billion MACs per second for 16 bit fixed-point processing. The fixed-point FFT performance is record-setting at 7,3 µs and what is claimed to be the industry's highest floating-point performance for a DSP, executing an FFT in 69 µs. The FFT is a quintessential algorithm used throughout real time signal processing applications. This unprecedented 32 bit speed is derived from the chip's ability to process 900 million floating-point operations per second (MFLOPS), an increase of 50% over ADI's SHARC DSPs.

Development environment

The TigerSHARC platform offers DSP designers a flexible development environment that supports both C and assembly language programming. It features robust and efficient C-compiler tools, and for time-critical inner loops, DSP programmers can use the machine's assembly language to guarantee high-performance code. The TigerSHARC platform, is claimed to be practical to program in assembly, with features such as an easy-to-learn algebraic assembly language syntax, predictable two-cycle delay for all computations, 128 fully interlocked, general-purpose registers, and branch prediction.

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