Analogue, Mixed Signal, LSI


Cascaded dual DDR memory power controllers

5 June 2002 Analogue, Mixed Signal, LSI

Intersil's Endura ISL6530 and ISL6531 dual pulse width modulation (PWM) regulator ICs are designed to power double data rate (DDR) synchronous dynamic random access memory (SDRAM) on computer motherboards and systems. The new power controllers are 5 V input devices and provide three regulated voltage sources: a VDDQ chip voltage that provides the main power to the memory, a Vref low-power reference source that tracks the middle point of VDDQ, and a VTT voltage source that powers parallel termination resistors and also tracks the middle point of the VDDQ voltage. These devices use a cascaded approach where the DDR memory line termination voltage, VTT, is created from the DDR memory voltage, VDDQ. The ISL6530 and ISL6531 come in 24-lead SOIC or 32-lead 5x5 mm MLF package.



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