Programmable logic vendors have now introduced devices with performance that rivals ASIC designs, without the cost of a $1-million mask set, or minimum volume requirements. To achieve this high-performance these devices contain a large quantity of programmable logic with embedded microprocessor cores, memory and advanced intellectual property (IP). These features provide significant benefits for the designer, such as reduced system development and the flexibility to make changes right up to production.
The devices, characterised as programmable system-on-chip (SoC) platforms, represent a dramatic technical breakthrough, but with all disruptive technologies come new design and verification challenges. These challenges require new and unique remedies.
New technology requires advanced methodology
The combination of large, complex IP blocks, hard and soft embedded processors and embedded software on a single chip, along with soaring transistor counts, tax the capabilities of traditional design methodologies. The design of these chips requires a new degree of sophistication, characterised by deeper, system-level design, concurrent hardware/software design and verification at all stages of the design process.
When hard or soft microprocessors are embedded on a programmable platform, designers face the difficult challenges associated with embedded software development. Design environments must include software compilers, software debuggers and hardware-connection probe tools that support both hard and soft processor core technologies. New system designs have multiple microprocessors on a board and the move is to multiple processors in a single device. To support these trends, software development suites must include compilers, embedded software and a debugger optimised for target processor architectures.
System-level design tools can guide system designers through hardware and software partitioning, facilitating the attachment of microprocessor cores and blocks of logic to platforms. But with modern programmable logic devices, there is a potentially huge divide between what can be put in the chip versus what can be verified to work. Bridging this gap requires the integration of many pieces of the hardware/software design and verification paradigm: software debugging, event-driven logic simulation and complex IP modelling.
Verification
As the design focus shifts from content creation to the challenges of evaluating, integrating and verifying multiple pre-existing blocks and software components, designers will have to deploy advanced verification solutions, such as co-verification. Hardware and software must be designed and verified in parallel. Programmable SoCs are so large and complex that re-designs in the future will incur even more significant delays than they already do today.
ASIC designers who use MPU cores such as ARM, MIPS and PowerPC, already employ hardware/software co-verification techniques to spot system design issues early in the development cycle. Mentor Graphics' Seamless product is the dominant tool in this sphere. Increasingly, such methodologies will be carried over into FPGA design.
Traditional simulation methods have also been enhanced to add new features that add advanced debugging capabilities, such as in the latest version of Mentor's ModelSim HDL simulator. With the increase in design sizes, bugs are becoming harder and harder to find and fix. New tools offer graphical debug capabilities help designers quickly trace design behaviour back to the source.
Synthesis
Many synthesis tools look at RTL code on a line-by-line basis and build up the design from low-level gates. With the increase in design size associated with large Programmable SoC devices, this approach becomes extremely time-consuming and does not deliver the highest quality of results. New approaches examine the intent of the RTL and build up the architecture of the design from large building blocks. This approach allows users to take full advantage of a new FPGA architecture, detecting architectural signatures and using algorithms optimised to deliver the best results.
New programmable devices have moved into the technology range where accuracy is everything. Rapid timing closure remains an ongoing goal and achieving this is strained by advanced technology developments, including 0,13-micron and below silicon technology and wire loads that consume 50-70% of circuit delay.
Small geometries and the increased role of interconnects in device behaviour require new synthesis methods. It becomes far more difficult to predict timing because the inter-connect delays are greater than the intrinsic gate delays. To solve new timing issues and guarantee a reliable design, synthesis tools must include timing engines and constraint entry systems designed to handle complex timing analysis.
Other methods for achieving timing closure include physical synthesis. Traditional physical synthesis approaches like rewriting the RTL, working with the constraints or maybe even floorplanning add value, but smarter synthesis algorithms that leverage actual physical data are required to help the designer keep pace with technology advancements and get their products to market faster. Automated algorithms such as re-timing, replication and re-synthesis add value especially when they are re-enforced with placement optimisation. After automation has done as much as possible, an interactive environment allows the user to close on those last few signals. This is the approach used by Mentor Graphics' Precision RTL synthesis tool.
Every chip goes onto a board
To complete a programmable platform system design requires chip and board design to be conducted in parallel. Concurrent design enables system engineers to synchronise the FPGA with the board, minimising inter-connectivity delay and accelerating system timing closure. Parallel design of the FPGA and the board allows designers to create faster, denser boards and to simulate the whole system. In many cases the programmable device will be used alongside standard microprocessors and DSPs. Models for these processors are also available in Mentor Graphics' Seamless product, which enables designers to use the same tool for both device and system level co-verification.
Innovation ahead
Market dynamics are changing as consumerisation squeezes project lifecycles down to months rather than years. With shorter product cycles, the flexibility of programmable logic is extremely advantageous. As FPGAs support limited but widespread products and platforms, design efforts will be more focused. Programmable SoC invites innovation: it puts complex silicon in the hands of most designers for the first time and it makes available unprecedented system design methodologies.
Innovation - driven by the large user base - will occur rapidly. Therefore, programmable technology will mature at a faster pace than ASICs. Consequently, programmable SoC and its supporting tools will develop quickly. Historically, it took more than ten years to put the tools in place for the typical ASIC design flow; adoption of those same tools for FPGA applications is happening much faster. Early ASIC applications have pipe-cleaned the tool flow for hardware/software design and verification, enabling EDA developers to rapidly deploy robust, proven tool flows for designing complex programmable SoC devices.
For more information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, [email protected]
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| Email: | [email protected] |
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