The demand for increased bandwidth and security in network infrastructure driven by growth in hybrid work and geographical distribution of networks is re-defining borderless networking. Led by AI/ML applications, the total port bandwidth for 400G (gigabits per second) and 800G is forecasted to grow at an annual rate of over 50%, according to 650 Group. This dramatic growth is expanding the transition to 112G PAM4 connectivity beyond just cloud data centre and telecom service provider switches and routers to enterprise ethernet switching platforms.
Microchip Technology Inc. has responded to this market inflection with the META-DX2 Ethernet PHY (physical layer) portfolio by introducing a new family of META-DX2+ PHYs. These are the industry’s first solution set to integrate 1,6T (terabits per second) of line-rate end-to-end encryption and port aggregation, to maintain the most compact footprint in the transition to 112G PAM4 connectivity for enterprise ethernet switches, security appliances, cloud interconnect routers and optical transport systems.
“Introduction of four new META-DX2+ Ethernet PHYs demonstrates our commitment to supporting the industry transition to 112G PAM4 connectivity powered by our META-DX retimer and PHY portfolio. In conjunction with our META-DX2L retimer, we now offer a complete chipset for all connectivity needs from retiming to advanced PHY functionality,” said Babak Samimi, corporate vice president of Microchip’s communications business unit. “By offering both hardware and software footprint compatibility, our customers can leverage architectural designs across their enterprise, data centre, and service provider switching and routing systems that can offer pay-as-you-need enablement of advanced features including end-to-end security, multi-rate port aggregation, and precision timestamping via software subscription model.”
META-DX2+ differentiated capabilities include:
• Dual 800 GbE, quad 400 GbE and 16x 100/50/25/10/1 GbE MAC/PHY.
• Integrated 1,6T MACsec/IPsec engines that offload encryption from packet processors, so systems can more easily scale up to higher bandwidths with end-to-end security.
• Greater than 20% board savings compared to competing solutions that require two devices to deliver the same 1,6T gearbox and hitless 2:1 mux modes.
• XpandIO enables port aggregation of low-rate Ethernet clients over higher speed Ethernet interfaces, optimised for enterprise platforms.
• ShiftIO feature, combined with a highly configurable integrated crosspoint, enables flexible connectivity between external switches, processors, and optics.
• Device variants with 48 or 32 Long Reach (LR) capable 112G PAM4 SerDes, including programmability to optimise power vs. performance.
• Support for Ethernet, OTN, Fibre Channel and proprietary data rates for AI/ML applications.
“As the industry transitions to a 112G PAM4 serial ecosystem for high-density routers and switches, line-rate encryption and efficient use of port capacity becomes increasingly important,” said Alan Weckel, founder and technology analyst at 650 Group. “Microchip’s META-DX2+ family will play an important role in enabling MACsec and IPsec encryption, optimising port capacity with port aggregation, and flexibly connecting routing/switching silicon to multi-rate 400G and 800G optics.”
| Tel: | +27 11 319 8600 |
| Email: | [email protected] |
| www: | www.avnet.com/wps/portal/silica |
| Articles: | More information and articles about Avnet Silica |
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version