Working with customers and design for manufacturing (DFM), the usual questions is “what’s the limit?” How thin can you make 10 layers, or what is the smallest hole for this 4 mm PCB? Very few people ask for reliability if we push the hole-to-thickness aspect ratio to the limit, or reduce the hole wall of copper to the minimum.
The question is always: what is your capability?
In most cases it is the component footprint that brings the designer into a situation where he needs to push limits.
Some examples are when you:
• Need one or more traces between the pads in a BGA area.
• Need connection from top to bottom but have very limited space through the stack-up.
• Sometimes there might be a need for impedance controlled traces with a return path in the next layer, which restricts sufficient hole-to-copper clearance in the ground plane layer.
• Need via-in-pad and capped vias in a plated layer where the design requires too thin a track and gap, leaving the PCB factory in a situation where nothing works optimally and in reality the finished PCB may have reliability issues, especially if the product needs multiple soldering operations and in an application environment with elevated temperatures.
The parameters that affect reliability are not only related to design for PCB fabrication, but are also very much related to thermal processes and the application environment. With that background I would like to give a few examples of dos and don’ts that put the end product’s reliability in jeopardy.
Hole-to-PCB-thickness aspect ratio
The question about aspect ratio comes up almost every week. Someone wants to know which factory has the best aspect ratio. This question poses several questions in response:
• What is the technology needed?
• How thick is the PCB?
• What hole size is needed to design this PCB?
• How big can the pads be?
The ping pong or ‘chicken or egg’ situation
Of course, the designer needs to know the answers to these questions to start his job, however you might find yourself in a ‘chicken or egg’ situation, where my questions in response lead in turn to more questions asked of me.
Some physics understanding lead us to these rules of thumb:
• Let the factory choose the hole size based on your available pad size and the required rest annular ring according to IPC Class 2 or 3.
• Copper pattern to hole registration can today be more easily achieved than pushing the aspect ratio. Both drilling and image accuracy have been improved greatly, while copper plating of small holes can still be a problem.
Key learning: Insufficient copper plating in via holes is a much higher reliability risk than annular ring violations.
The effect of filled and capped vias
A change from etched layers to plated layers, and in the worst case adding capped vias, can bring down a design from a reliable solution to a show stopper. I had one example of an HDI 32 layer that we had tuned in by stack-up to meet impedance constraints, however the design was quite tough.
Then the designer finally said, “I need those through-hole vias capped. I need ‘via in pad’ – it is the only way to route myself out of this fine pitch BGA!” Wow… that ruined the whole thing. Suddenly we needed another copper plating process.
Thicker copper means etching of those 75 micron traces, and with 75 microns, gaps becomes impossible. Because we push boundaries we also challenge reliability. The more processes we add to an already tight design, the more we increase the risk of defects, either in assembly or, in the worst case, in the final application.
In this example, it would be much better to replace the through vias with a combination of blind and buried vias.
Key Learning: Copper filled microvia is a much better solution for fine line patterns than filled and capped through-holes.
Inner layer hole-to-copper
In some tight high layer count designs we see that the designer removes non-functional pads to make place for inner layer tracking, close to the via holes. Often this is a good solution, but beware! Drilling of holes in a PCB is a mechanical process that stresses the base material. As the drill bit is being used to drill many holes, the tool becomes less sharp with each hole drilled, until we reach the limit of acceptable roughness.
Then comes the question of what is acceptable, and what is preferred? We need some roughness to get a good adhesion between the copper barrel and the hole wall. But this slight roughness should not open pores into the material that enable chemistry to enter and create what we call wicking, a conductive spike from the copper barrel and into the material.
Always remember to bring the risk factor into discussion
In the standard, IPC-6012, the size of such spikes can be up to 80 microns for Class 3 and 100 microns for Class 2 products. So, if we remove the pad on the inner layer to leave room for a track as close as 150 microns we are in danger. If the factory can allow 80 micron wicking and we know that hole-to-copper tolerance is around 50 microns (in fact often 100 microns) we are suddenly in danger of a direct contact. And remember, wicking is often a starting point for conductive anodic filaments (CAF), which manifest themselves over time.
So what can we learn from this? Investigate the PCB factory’s capability with care. Some PCB factories will warn you, but in many cases the customer is in such need of more room that the focus of discussion is on capability and not risk of failure in the application.
Key learning: Make sure to bring the risk factor into discussion and be open to better solutions that could replace the through-hole via with smaller blind and buried vias in combination, and thereby provide more room for inner layer traces.
From these examples we can see that a factory’s capability does not necessarily mean you can go to the limit, and in the worst case combine capability limits that in reality are impossible combinations. On the other hand, if you really need to push limits, make sure to ask the right questions.
Don’t just ask for technical capabilities, but make sure to discuss combinations and how your solution affects risk of failure with the multiple heat cycles required to assemble the product, and the risk of failure in the final application.
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