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Microsemi unveils PolarFire FPGA
22 March 2017, Programmable Logic

Microsemi unveiled the new cost-optimised PolarFire field programmable gate array (FPGA) product family, delivering what the firm claims is the industry’s lowest power at mid-range densities with 12,7 Gbps serialiser/deserialiser (SerDes) transceivers as well as best-in-class security and reliability. The FPGA product family is ideal for a wide range of applications within wireline access networks and cellular infrastructure, defence and commercial aviation markets, as well as Industry 4.0 which includes the industrial automation and Internet of Things (IoT) markets.

Today’s cellular infrastructure and wireline access networks are facing a rapid transformation, having to deliver terabytes of high-value content to consumers while reducing operational and capital expenditure, as well as reducing their thermal and carbon footprints. PolarFire FPGAs provide cost-effective bandwidth processing capabilities for the increasing number of converged 10 Gpbs ports with a low power footprint. They also address the market’s growing concerns over tangible cyber security threats as well as reliability concerns that face deep submicron SRAM-based FPGAs as they relate to single event upsets (SEUs) in their configuration memory.

In collaboration with Silicon Creations, Microsemi has developed a 12,7 Gbps transceiver that consumes less than 90 mW at 10 Gbps. The devices boast low device static power of 34 mW at 100K logic elements (LEs), zero inrush current and unique Flash*Freeze mode for standby power of 15 mW at 25°C. Microsemi also provides customers with a power estimator to analyse power consumption of their designs. After implementation, the SmartPower Analyser can be used to access full design power.

PolarFire also provides inherent immunity to configuration SEUs. Additional features to aid with reliability include built-in single error correction and double error detection (SECDED) as well as memory interleaving on large static random access memory (LSRAMs), and system controller suspend mode for safety-critical designs.

Leveraging Microsemi’s expertise in security, the new FPGAs offer Cryptography Research Incorporated (CRI) patented differential power analysis (DPA) bitstream protection, integrated physically unclonable function (PUF), 56 KB of secure embedded non-volatile memory (eNVM), built-in tamper detectors and countermeasures, true random number generators, integrated Athena TeraFire EXP5200B Crypto Co-processors (Suite B capable) and a CRI DPA counter-measures pass-through licence.

The Libero SoC Design Suite offers comprehensive, easy to learn, easy to adopt development tools for designing with PolarFire FPGAs. The suite includes a complete design flow with Synopsys Synplify Pro synthesis and Mentor Graphics ModelSim Pro mixed-language simulation with advanced constraints management, and Microsemi’s differentiated FPGA debugging suite, SmartDebug. Popular IP solutions for 1G Ethernet, 10G Ethernet, JESD204B, DDR memory interfaces, AXI4 interconnect IPs and others are available for use with PolarFire devices.


Credit(s)
Supplied By: ASIC Design Services
Tel: +27 11 315 8316
Fax: +27 11 315 1711
Email: info@asic.co.za
www: www.asic.co.za
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Further reading:

  • RFSoC architecture by Xilinx
    14 November 2018, Avnet South Africa, Telecoms, Datacoms, Wireless, Programmable Logic
    Xilinx rolled out its Zynq UltraScale+ RFSoC family, an architecture integrating the RF signal chain into a system-on-chip (SoC) for high-performance RF applications. Based on the 16 nm UltraScale+ ...
  • RISC-V based FPGA architecture
    14 November 2018, Altron Arrow, Programmable Logic
    Microchip, via its Microsemi Corporation subsidiary, announced an extension to its Mi-V ecosystem by unveiling the architecture for a new class of SoC FPGAs at the RISC-V Summit during December 2018. ...
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  • PolarFire FPGAs from Microsemi
    15 November 2017, ASIC Design Services, Electronics Technology
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  • IDE supporting RISC-V instruction set architecture
    19 July 2017, ASIC Design Services, Design Automation
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  • Electronic Product Creation Seminars
    19 July 2017, ASIC Design Services, News
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  • Xilinx SoCs get RF-class analog
    19 April 2017, Avnet South Africa, Programmable Logic
    Xilinx is claiming a disruptive integration and architectural breakthrough for 5G wireless with the infusion of RF-class analog technology into its 16 nm All Programmable MPSoCs. The company says its ...
  • DFT tool for Mentor Graphics PADS
    19 April 2017, ASIC Design Services, Design Automation
    Developed by XJTAG, the free DFT Assistant software for Mentor Graphics’ PADS platform increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design environment. Printed ...
  • ISP Flash configuration for ARM-based FPGAs
    9 November 2016, ASIC Design Services, Programmable Logic
    XJTAG has extended the capability of its high-speed in-system programming (ISP) technology, XJFlash. The solution effectively brings the benefits of XJFlash to memory devices connected to the processor ...

 
 
         
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