DFT tool for Mentor Graphics PADS - 19 April 2017 - ASIC Design Services

Developed by XJTAG, the free DFT Assistant software for Mentor Graphics’ PADS platform increases the design for test (DFT) and debug capabilities of the schematic capture and PCB design environment.

Printed circuit boards (PCBs) are increasingly densely populated and access to pins under many packages, such as ball grid arrays (BGA), is virtually impossible. JTAG was designed to solve the problem of access and so it is now vitally important to get the JTAG chain right at the design stage. Failure to identify and fix design errors at an early stage can result in a board re-spin and a costly delay to a project. XJTAG DFT Assistant helps validate correct JTAG chain connectivity, through full integration with the PADS schematic capture environment.

“PADS products now include the XJTAG DFT Assistant that provides engineers with a free, easy-to-use interface to check if JTAG chains are correctly connected and terminated at the schematic capture stage, long before the PCB is produced,” said Jim Martens, product marketing manager, PADS Solutions Group. “By detecting and correcting these faults earlier, companies do save both time and money. This software is free for PADS users of VX.2.1 or higher and can be downloaded from www.xjtag.com/pads.”

The XJTAG DFT Assistant comprises of two key elements: the XJTAG Chain Checker, and the XJTAG Access Viewer.

XJTAG Chain Checker identifies common errors in a JTAG scan chain, such as incorrectly connected test access ports (TAPs). A single connection error would inhibit an entire scan chain from working. The checker identifies connection errors and reports them to the developer during the design process. Incorrectly terminated TAPs are also identified.

XJTAG Access Viewer overlays the extent of boundary scan access onto the schematic diagram, allowing users to instantly see which components are accessible using boundary scan, and where test coverage could be further extended. Engineers can highlight the nets individually to show read, write, power/ground and the nets that don’t have any JTAG access on the schematic.

While the first prototype is being manufactured, XJTAG DFT Assistant allows engineers to export a preliminary XJTAG project from the PADS schematic capture environment to the XJTAG development software, where additional tests can be developed. These can then be used to test real hardware, as soon as it’s available.

For more information contact ASIC Design Services, +27 (0)11 315 8316, info@asic.co.za, www.asic.co.za