The latest version of Mentor Graphics' FPGA Advantage integrated design environment features a new design cockpit that integrates recent updates to the HDL Designer Series, ModelSim and Precision RTL Synthesis products.
Says Simon Bloch, FPGA design division, Mentor Graphics: "Mentor Graphics continues to execute on a strategy that provides individual designers and design teams with completely interoperable tool flows that manage the complexity of today's FPGAs. We were the first to integrate design creation, synthesis, and simulation and with FPGA Advantage 6.1 we look to extend data connections with more tools in the FPGA design flow."
Version 6.1's intuitive design cockpit simplifies design creation and begins analysis from the start of a design project. Textual, tabular and graphical editors can be combined with design elements from ModuleWare, previous designs, external IP providers, as well as IP from FPGA vendors' macro and IP libraries. Combined, these elements provide a rich variety of design creation means to rapidly construct the FPGA. In addition, team design and the analysis capabilities of the data provide easy navigation with the ability to search and organise data to help understand design content.
FPGA Advantage 6.1 provides several options for verifying a complex design. The tool accelerates the functional design development by focusing on optimising the entire design creation, verification and modification design loop while providing the designer the flexibility to verify the way that matches his design style. Dynamic animation features allow to view simulation results within the design creation editor to reveal high-level design and functional behaviour, as well as enables designers to debug a design exactly as it was entered.
Advanced synthesis capabilities assist in implementing high-complexity FPGA designs. Integrating precision RTL synthesis, FPGA Advantage includes capabilities that transform vendor-independent HDL code into a structural design that effectively leverages specific design architectures. Because it is vendor independent, design teams can consider several component cost alternatives to optimise profit margins.
The IDE's synthesis engine has a new algorithm (Architecture Signature Extraction) that provides data on how to best use the FPGA fabric as well as the available embedded memory, DSP block or clock management resources. The algorithm optimises signal paths to achieve optimum timing requirements.
Since every design must be documented, FPGA Advantage also automatically documents all stages of the flow using Microsoft object linking and embedding (OLE) and HTML export formats.
Every FPGA must be placed on a printed circuit board. Integrating complex FPGAs onto a PCB may result in expensive PCB re-spins due to the introduction of manual data entry errors. Mentor Graphics says it is the only company with an integrated FPGA and PCB design flow that automates the physical chip and board integration process.
The design tool flow supports Windows/2000/XP/NT 4.0; Sun Solaris 8, HP-UX 11.00 or 11.11; and Linux Red Hat 7.3.
For more information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, [email protected].
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