Analog timing chip delivers six ultra low-jitter output clocks

Telecoms, Datacoms, Wireless, IoT

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27 August 2003 Telecoms, Datacoms, Wireless, IoT

Zarlink Semiconductor's high-performance analog PLL timing chip for optical line cards operating at up to OC-192 (Optical Carrier level 192) rates has six output clocks and a jitter performance that surpasses industry specifications.

Analog PLLs perform timing and synchronisation functions in communications equipment, including SONET/SDH line cards in network core, metro, edge, and access equipment. Zarlink's flexible ZL30414 analog PLL accepts one clock signal and simultaneously outputs six low-jitter, higher-frequency clocks.

Jitter is a short-term variation in clock timing caused by noise from various sources, such as power supplies, and thermal noise from other components. Noise can broaden the clock signal, making it difficult for the receiving equipment to discern the original signal, which can in turn cause data errors. Ultra-low jitter, measured in picoseconds (trillionths of a second), is crucial in systems operating at high speeds. For OC-192/STM-64 systems operating at 10 Gbps, the jitter budget - the amount of timing variation allowed from various sources - is extremely small, making the performance of timing devices critical.

The jitter performance of the ZL30414 analog PLL meets Telcordia and ITU-T requirements for OC-192/STM-64 systems. Jitter performance is 0,52 ps r.m.s., providing significant margin against Telcordia's GR-253-CORE requirement of 1 ps r.m.s. Also, it delivers a peak-to-peak jitter performance of 6,95 ps, surpassing ITU-T G.813 Option 1 and 2 requirements for a maximum peak-to-peak jitter performance of 10 ps for STM-64 rates.

For more information contact Memec SA, 011 897 8600.

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Analog timing chip delivers six ultra low-jitter output clocks

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