Synplicity says it has enhanced its Certify ASIC RTL prototyping software to further accelerate the ASIC verification process. The new version offers enhanced quick partitioning technology (QPT) with certify pin multiplier (CPM) support that provides designers with an automated flow for prototyping an ASIC design using an off-the-shelf FPGA board or other hardware.
To further optimise its ASIC prototyping capabilities, the Certify 6.3 software incorporates the latest compilers and mappers from Synplicity's Synplify Pro advanced FPGA synthesis software, providing the same language support for VHDL and Verilog.
"Fitting an ASIC design onto an FPGA board is a complex problem," said Brian Caslis, director of marketing for the Certify product line at Synplicity. "Using a bigger board with more FPGA devices may not address the problem because as the ASIC is partitioned across the FPGAs, I/O interconnects may actually increase. We believe the Certify tool's new ability to automatically multiplex the I/O when necessary will result in huge time savings, and enable more designers to leverage FPGAs to prototype their ASIC designs."
The Certify software also now provides support for the Xilinx Spartan III and Altera Stratix GX device families and enables designers to mix both Altera APEX and Stratix devices on a single board. This allows designers to lower their overall prototyping costs by using both high-performance and lower-cost devices in the same hardware prototyping environment.
Synplicity has also announced that AMO and EVE have joined its Partners in Prototyping Program. The program brings together leading hardware, software and design service providers to offer a proven methodology for building FPGA-based prototypes, speeding the overall ASIC design and development cycle. Once these complementary solutions are proven to work with the Certify software tool, the documentation and technical information are then made available on the Partners in Prototyping Web page on Synplicity's Web site.
AMO's Venus-X prototyping platform, with widely configurable hardware concept and massive external connectivity, enables accelerated ASIC verification, hardware-assisted software debugging, and implementation of massive parallel algorithms at an early stage of product development with a system complexity of expandable 48 MGates. EVE provides a hardware-assisted verification platform used to accelerate the verification process of ASIC designs and the software development cycle for embedded software designs. Installed on a designer's desktop, EVE ZeBu verifies designs up to 12 million ASIC equivalent gates, offering the same debugging capabilities found in high-end emulation systems.
For more information contact Franco Giangregorio, Parsec, 012 349 2282, [email protected]
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