Simulator supports Stratix II device family
21 April 2004
Design Automation
Aldec has announced support for Altera's latest high density Stratix II FPGA device family. Support for Stratix II's innovative logic structure is available in Aldec's graphical design entry tool, design flow manager, as well as its mixed-VHDL and Verilog simulator. The Stratix II devices are also being incorporated into Aldec's hardware acceleration tools which have support for multiple Stratix II devices on a single board, providing ASIC designers the multimillion gate capacity required to achieve RTL acceleration.
"Aldec customers are seeking support for the highest density FPGA architectures. With the release of Altera's Stratix II family, we can not only offer them fast RTL, gate-level, and timing simulation run times, but we are also incorporating the latest Stratix II devices in our hardware acceleration solutions. This will provide ASIC customers with access to additional gates in order to support our RTL acceleration solution," stated David Rinehart, director of marketing at Aldec.
"As a member of Altera's Commitment to Cooperative Engineering Solutions (ACCESS) program, Aldec has allowed mutual customers to have direct access to our latest FPGA devices from Aldec's mixed-HDL simulation solution. In addition to traditional RTL flows, we are also integrated by Aldec's usage of our latest high-density devices in their RTL accelerator solutions," stated James Smith, director of EDA vendor relationships, Altera.
Developed with an innovative new logic structure, Stratix II devices offer over twice the logic density and 50% higher performance at 40% lower cost than first-generation Stratix devices. Its new logic structure allows designers to conserve device resources by packing more functionality into a smaller area.
Aldec's Active-HDL (Altera Edition) is a Windows-based product that is a completely integrated, high performance HDL design entry and simulation environment for all Altera devices. It supports languages including: VHDL, Verilog, C/C++, Celoxica's Handel-C as well as EDIF netlist simulation from one universal design entry and verification environment simulation.
For more information contact Franco Giangregorio, Parsec, 012 349 2282, [email protected]
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