Renesas Technology has developed a 5-layer stacked SiP (system in package) that incorporates a SuperH microprocessor, logic LSI chip and memory chips in a single package.
Increasing the current maximum number of stacked chips in a SiP from three to five, Renesas says it offers users a wider choice of chip combinations while enabling the mounting area to be reduced by approximately 70 to 80%. The device is suited for digital consumer products, such as digital video and still cameras, PDAs and mobile phones.
The 5-layer stacked SiP enables greater flexibility in creating a suitable configuration for a particular system. The stack structure enables the mounting area to be reduced compared with the use of individual packages. The device can also reduce system development times; using existing chips, the SiP can be developed in approximately five to six weeks from final specification to sample delivery, claims the company. The SiP also offers lower EMI noise and therefore more stable high-speed operation due to the reduced wiring length between chips.
Renesas currently mass-produces flat-type SiPs and 2-layer/3-layer stacked SiPs incorporating microcomputer chips such as a SuperH microprocessor, M16C or M32C microcontroller, and memory, such as synchronous DRAM or flash memory, in a single package. It is pursuing the development of SiPs as part of its SIP (solution integrated product) offering to users.
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