Lattice Semiconductor recently launched its third generation of non-volatile FPGAs, the LatticeXP2 family.
The product family consists of five members, with capacities from 5K to 40K 4-input look up tables (LUTs). Embedded block memory provides up to 885 Kbits in 18 Kbit dual-port blocks. For small scratch pad memories, LUTs can also be converted into small, distributed memory blocks. To support increasingly common DSP applications, up to 12 sysDSP blocks provide hardwired high-performance pipelined multiply and accumulate functions. The devices have up to four phase locked loops (PLLs) that allow designers to align and synthesise clocks as required in their designs.
The LatticeXP2 family uses a low 1,2 V core voltage and incorporates an enhanced circuit design so that, despite the largest device density doubling to 40K LUTs over previous models, static power consumption has increased by only 34%.
I/O capacities for the family range from 86 to 540 pins. Flexible I/O buffers support the most popular I/O standards, including LVCMOS, SSTL, HSTL and LVDS. These buffers are supported by pre-engineered I/O logic that simplifies the implementation of double data rate (DDR) and source synchronous standards. This combination provides support for DDR2 memory interfaces at 400 Mbps, high performance ADC/DACs at up to 750 Mbps and 7:1 LVDS display interfaces at above 600 Mbps. LatticeXP2 devices are available in a number of space saving chip scale ball grid array (csBGA) packages, thin as well as standard fine pitch ball grid array (ftBGA and fpBGA) packages and popular TQFP and PQFP options.
The LatticeXP2 devices incorporate an instant-on capability, by employing embedded flash memory blocks that transfer the device configuration into SRAM cells in a parallel fashion, to achieve device logic availability in approximately 1 millsecond. A one-time-programmable (OTP) mode is provided for protection against unauthorised programming. Optional 128-bit AES encryption can be used to secure programming data being passed into the device.
The LatticeXP2 devices allow field updates and bug fixes to be performed and, to protect against incomplete new configuration downloads due to communication or system failures during field updates, a 'golden configuration' can be stored in an optional external SPI boot memory and the device can boot automatically from this configuration if bitstream errors are detected. They also support TransFR (transparent field reconfiguration) technology that allows new configurations to be loaded into the LatticeXP2 device while the I/O states are precisely controlled, allowing new configurations to be applied while the target system continues to operate.
| Tel: | +27 11 923 9600 |
| Email: | info@arrow.altech.co.za |
| www: | www.altronarrow.com |
| Articles: | More information and articles about Altron Arrow |
© Technews Publishing (Pty) Ltd | All Rights Reserved
printer friendly version