Design Automation


Test-bench automation tool exploits distributed computing

23 July 2008 Design Automation

Mentor Graphics has announced the availability of an enhancement to inFact, the award-winning intelligent test-bench automation tool. The latest version of inFact now enables large simulations to be automatically distributed across up to 1000 CPUs, extending non-redundant sequence generation to entire simulation server farms.

inFact achieves high functional coverage by algorithmically traversing multiple rule-graphs and synthesising test-bench sequences on-the-fly during simulation. The rule-graphs are derived from interface descriptions, bus protocols, functional specifications or test plans. While rule-graphs are much smaller than conventional test-benches, they allow large quantities of sequences to be generated. However, unlike traditional constrained random test techniques, rule-graphs enable non-redundant sequence generation, eliminating waste of simulation time and resources.

A spatial distribution algorithm prevents repetition of sequences on any given simulation CPU, and a modulo-N algorithm prevents repetition of sequences across the entire simulation farm. The same simulation of millions of sequences that requires one thousand hours of run-time on a single CPU can be completed in just minutes longer than ten hours on a simulation farm of one hundred similar simulation CPUs.

However, the power of rule-graphs for production simulation is only partially realised when it assumes that all simulation CPUs are equivalent, all are available for distribution 100% of the time, and that all test-bench sequences require the same amount of simulation time. In a more realistic situation, not all CPUs in a server farm may be equally configured, not all may be available for the duration of a simulation run, and every test-bench sequence may take a different amount of time to simulate.

To address these complexities, inFact breaks up the universe of sequences into smaller virtual slices and assigns a new slice to each simulation CPU when it has completed the previous slice or when it becomes available altogether. This provides an automatic load-balancing effect, preventing the situation where one simulation CPU finishes quickly and waits idly while others finish. It also uses every available simulation resource efficiently, including CPUs that become available after finishing other jobs.



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