Design Automation


Test-bench automation tool exploits distributed computing

23 July 2008 Design Automation

Mentor Graphics has announced the availability of an enhancement to inFact, the award-winning intelligent test-bench automation tool. The latest version of inFact now enables large simulations to be automatically distributed across up to 1000 CPUs, extending non-redundant sequence generation to entire simulation server farms.

inFact achieves high functional coverage by algorithmically traversing multiple rule-graphs and synthesising test-bench sequences on-the-fly during simulation. The rule-graphs are derived from interface descriptions, bus protocols, functional specifications or test plans. While rule-graphs are much smaller than conventional test-benches, they allow large quantities of sequences to be generated. However, unlike traditional constrained random test techniques, rule-graphs enable non-redundant sequence generation, eliminating waste of simulation time and resources.

A spatial distribution algorithm prevents repetition of sequences on any given simulation CPU, and a modulo-N algorithm prevents repetition of sequences across the entire simulation farm. The same simulation of millions of sequences that requires one thousand hours of run-time on a single CPU can be completed in just minutes longer than ten hours on a simulation farm of one hundred similar simulation CPUs.

However, the power of rule-graphs for production simulation is only partially realised when it assumes that all simulation CPUs are equivalent, all are available for distribution 100% of the time, and that all test-bench sequences require the same amount of simulation time. In a more realistic situation, not all CPUs in a server farm may be equally configured, not all may be available for the duration of a simulation run, and every test-bench sequence may take a different amount of time to simulate.

To address these complexities, inFact breaks up the universe of sequences into smaller virtual slices and assigns a new slice to each simulation CPU when it has completed the previous slice or when it becomes available altogether. This provides an automatic load-balancing effect, preventing the situation where one simulation CPU finishes quickly and waits idly while others finish. It also uses every available simulation resource efficiently, including CPUs that become available after finishing other jobs.



Credit(s)



Share this article:
Share via emailShare via LinkedInPrint this page

Further reading:

ST’s graphical no-code design software
Design Automation
MEMS-Studio is a complete desktop software solution designed to develop embedded AI features, evaluate embedded libraries, analyse data, and design no-code algorithms for the entire portfolio of ST’s MEMS sensors.

Read more...
PolarFire SoC FPGAs achieve AEC-Q100 qualification
ASIC Design Services DSP, Micros & Memory
Microchip Technology’s PolarFire SoC FPGAs have earned the Automotive Electronics Council AEC-Q100 qualification.

Read more...
LibGSM – A powerful, modular GSM library
eiTech Systems Design Automation
Whether you are building SMS, MQTT, HTTP or other GSM-based applications, eiTech’s LibGSM library helps streamline development with its carefully structured design.

Read more...
NECTO Studio V7.2 IDE with code assistant
Design Automation
MIKROE recently announced that NECTO Studio 7.2 IDE now includes NECTO Code Assistant, an AI tool that enables users to create code for multi-Click projects.

Read more...
MPLAB unified compiler licenses
Design Automation
Offering an efficient way to manage multiple licenses, Microchip Technology has launched MPLAB XC unified compiler licenses for its MPLAB XC8, XC16, XC-DSC and XC32 C compilers.

Read more...
MPLAB PICkit Basic
ASIC Design Services Design Automation
To make its robust programming and debugging capabilities accessible to a wider range of engineers, Microchip Technology has launched the MPLAB PICkit Basic in-circuit debugger.

Read more...
Case Study: Siemens Valor automation solution
ASIC Design Services Editor's Choice Manufacturing / Production Technology, Hardware & Services
Electronics manufacturer BMK used Siemens Valor to enhance accuracy and speed up bill-of-materials quotations.

Read more...
Accelerating RF PCB design in a 5G world
ASIC Design Services Editor's Choice Design Automation
Billions of IoT devices coming online in the coming years will require RF design capabilities that support ultra-fast 5G speeds.

Read more...
XJLink-PF40 JTAG controller
ASIC Design Services Test & Measurement
XJTAG, a specialist in electronic testing, has released its new XJLink-PF40 JTAG controller together with version 4 of its popular PCB software testing suite.

Read more...
NECTO Studio has been updated
Design Automation
NECTO Studio V7.1 IDE from MIKROE now includes full programmer and debug support for Microchip tools and also adds support for Microchip’s SAM MCU and STMicroelectronics’ STM32L4 series of ultra-low-power MCUs.

Read more...