Design Automation


Test-bench automation tool exploits distributed computing

23 July 2008 Design Automation

Mentor Graphics has announced the availability of an enhancement to inFact, the award-winning intelligent test-bench automation tool. The latest version of inFact now enables large simulations to be automatically distributed across up to 1000 CPUs, extending non-redundant sequence generation to entire simulation server farms.

inFact achieves high functional coverage by algorithmically traversing multiple rule-graphs and synthesising test-bench sequences on-the-fly during simulation. The rule-graphs are derived from interface descriptions, bus protocols, functional specifications or test plans. While rule-graphs are much smaller than conventional test-benches, they allow large quantities of sequences to be generated. However, unlike traditional constrained random test techniques, rule-graphs enable non-redundant sequence generation, eliminating waste of simulation time and resources.

A spatial distribution algorithm prevents repetition of sequences on any given simulation CPU, and a modulo-N algorithm prevents repetition of sequences across the entire simulation farm. The same simulation of millions of sequences that requires one thousand hours of run-time on a single CPU can be completed in just minutes longer than ten hours on a simulation farm of one hundred similar simulation CPUs.

However, the power of rule-graphs for production simulation is only partially realised when it assumes that all simulation CPUs are equivalent, all are available for distribution 100% of the time, and that all test-bench sequences require the same amount of simulation time. In a more realistic situation, not all CPUs in a server farm may be equally configured, not all may be available for the duration of a simulation run, and every test-bench sequence may take a different amount of time to simulate.

To address these complexities, inFact breaks up the universe of sequences into smaller virtual slices and assigns a new slice to each simulation CPU when it has completed the previous slice or when it becomes available altogether. This provides an automatic load-balancing effect, preventing the situation where one simulation CPU finishes quickly and waits idly while others finish. It also uses every available simulation resource efficiently, including CPUs that become available after finishing other jobs.



Credit(s)



Share this article:
Share via emailShare via LinkedInPrint this page

Further reading:

Accelerate development of AI-enabled embedded systems
Design Automation
ADI’s CodeFusion Studio (CFS) is a modern embedded software development platform aimed at accelerating the creation of AI-enabled embedded systems.

Read more...
Introducing STM32CubeMX2
Altron Arrow Design Automation
STMicroelectronics has launched STM32CubeMX2, a new evolution of its popular configuration and code generation tool for STM32 microcontrollers.

Read more...
Miniature xtal for critical timing
ASIC Design Services Telecoms, Datacoms, Wireless, IoT
Microchip’s EX-423 Evacuated Miniature Crystal Oscillator is a compact, low-power timing solution designed for applications that demand high stability, accuracy, and long-term reliability.

Read more...
AI assistant for STM32 developers
Design Automation
The STMicroelectronics STM32 Sidekick is an AI-driven assistant fully integrated into the STM32 ecosystem designed to streamline embedded development using STM32 microcontrollers.

Read more...
Connected without limits: An engineering perspective on Altron Arrow’s wireless ecosystem
Altron Arrow Editor's Choice Design Automation
Wireless connectivity is no longer a supporting technology, but rather, a core design consideration that underpins modern electronic systems across industries.

Read more...
Next-gen robotic systems initiative
EBV Electrolink Design Automation
EBV Elektronik recently introduced MOVE – Driving Robotics Forward, a new initiative designed by EBV Elektronik‘s Embedded Solutions team to support the development of next-generation robotic systems.

Read more...
Reliable isolation for modern networks
ASIC Design Services Computer/Embedded Technology
The Pro-Tek5 PTI Series delivers reinforced 5 kV Ethernet isolation for applications that demand robust protection, reliable signal integrity, and full IEEE802.3 performance.

Read more...
Reference design for NB-IoT plus GNSS
Altron Arrow Design Automation
ST Microelectronics’ STDES-ST87M01IGN is a reference design for the ST87M01 NB-IoT + GNSS module, implemented on a 2-layer FR4 PCB (90 x 60 x 1,6 mm).

Read more...
ARINC 429 line driver evaluation board
ASIC Design Services DSP, Micros & Memory
Holt Integrated Circuits have announced the release of the ADK-85104 Evaluation Board, a compact, ready-to-use platform designed to help engineers rapidly evaluate and characterise Holt’s HI-85104.

Read more...
ST welcomes STM32Cube AI Studio
Design Automation
STMicroelectronics has introduced STM32Cube AI Studio, a new desktop software environment designed to simplify the deployment of artificial intelligence on STM32 microcontrollers.

Read more...









While every effort has been made to ensure the accuracy of the information contained herein, the publisher and its agents cannot be held responsible for any errors contained, or any loss incurred as a result. Articles published do not necessarily reflect the views of the publishers. The editor reserves the right to alter or cut copy. Articles submitted are deemed to have been cleared for publication. Advertisements and company contact details are published as provided by the advertiser. Technews Publishing (Pty) Ltd cannot be held responsible for the accuracy or veracity of supplied material.




© Technews Publishing (Pty) Ltd | All Rights Reserved