Design Automation


Test-bench automation tool exploits distributed computing

23 July 2008 Design Automation

Mentor Graphics has announced the availability of an enhancement to inFact, the award-winning intelligent test-bench automation tool. The latest version of inFact now enables large simulations to be automatically distributed across up to 1000 CPUs, extending non-redundant sequence generation to entire simulation server farms.

inFact achieves high functional coverage by algorithmically traversing multiple rule-graphs and synthesising test-bench sequences on-the-fly during simulation. The rule-graphs are derived from interface descriptions, bus protocols, functional specifications or test plans. While rule-graphs are much smaller than conventional test-benches, they allow large quantities of sequences to be generated. However, unlike traditional constrained random test techniques, rule-graphs enable non-redundant sequence generation, eliminating waste of simulation time and resources.

A spatial distribution algorithm prevents repetition of sequences on any given simulation CPU, and a modulo-N algorithm prevents repetition of sequences across the entire simulation farm. The same simulation of millions of sequences that requires one thousand hours of run-time on a single CPU can be completed in just minutes longer than ten hours on a simulation farm of one hundred similar simulation CPUs.

However, the power of rule-graphs for production simulation is only partially realised when it assumes that all simulation CPUs are equivalent, all are available for distribution 100% of the time, and that all test-bench sequences require the same amount of simulation time. In a more realistic situation, not all CPUs in a server farm may be equally configured, not all may be available for the duration of a simulation run, and every test-bench sequence may take a different amount of time to simulate.

To address these complexities, inFact breaks up the universe of sequences into smaller virtual slices and assigns a new slice to each simulation CPU when it has completed the previous slice or when it becomes available altogether. This provides an automatic load-balancing effect, preventing the situation where one simulation CPU finishes quickly and waits idly while others finish. It also uses every available simulation resource efficiently, including CPUs that become available after finishing other jobs.



Credit(s)



Share this article:
Share via emailShare via LinkedInPrint this page

Further reading:

ARINC 429 line driver evaluation board
ASIC Design Services DSP, Micros & Memory
Holt Integrated Circuits have announced the release of the ADK-85104 Evaluation Board, a compact, ready-to-use platform designed to help engineers rapidly evaluate and characterise Holt’s HI-85104.

Read more...
ST welcomes STM32Cube AI Studio
Design Automation
STMicroelectronics has introduced STM32Cube AI Studio, a new desktop software environment designed to simplify the deployment of artificial intelligence on STM32 microcontrollers.

Read more...
NeoCortec introduces new NeoGW software
Design Automation
This is a powerful multiplatform open-source solution designed to streamline integration between the NeoMesh network and upper-level systems, whether deployed in the cloud or on-premise environments.

Read more...
Keil Studio now in VSCode
Design Automation
Keil Studio, Arm’s latest IDE, now integrates embedded development tools directly into Visual Studio Code providing features like seamless industry tool integration, version control, and a CLI for CI workflows.

Read more...
Inventec enhances design for manufacturing excellence with Siemens’ software
ASIC Design Services Manufacturing / Production Technology, Hardware & Services
Siemens recently announced that Inventec Corporation has adopted Siemens’ Valor NPI software and Process Preparation X solutions from the Siemens Xcelerator portfolio to strengthen its design-for-manufacturing efficiency.

Read more...
Quad-Apollo MxFE reference design
Design Automation
The Quad-Apollo MxFE reference design exemplifies a complete, high-performance platform for every-element direct-RF sampling digital beamforming using Analog Devices’ Apollo mixed-signal front-end technology.

Read more...
Siemens acquires Canopus AI
ASIC Design Services News
The acquisition extends Siemens’ comprehensive EDA software portfolio with computational metrology and inspection to help chipmakers solve critical technical challenges in semiconductor manufacturing.

Read more...
MIKROE signs multi-year deal with Renesas
Dizzy Enterprises Design Automation
MIKROE has signed a multi-year MCU development tool support deal with Renesas, which commits MIKROE to providing development tools for 500 of Renesas’ most popular MCUs.

Read more...
Future Electronics and SnapMagic announce CAD model integration to support faster design cycles
Future Electronics Design Automation
Engineers can now download verified symbols, footprints, and 3D models directly from supported product pages, enabling a smoother transition from component selection to PCB layout.

Read more...
Pulsonix 14.0 advances design
Design Automation
Pulsonix’s latest PCB design software platform further strengthens simulation and brings significant enhancements in mechanical-electrical 3D integration, smarter comparison tools, and enhanced usability features.

Read more...









While every effort has been made to ensure the accuracy of the information contained herein, the publisher and its agents cannot be held responsible for any errors contained, or any loss incurred as a result. Articles published do not necessarily reflect the views of the publishers. The editor reserves the right to alter or cut copy. Articles submitted are deemed to have been cleared for publication. Advertisements and company contact details are published as provided by the advertiser. Technews Publishing (Pty) Ltd cannot be held responsible for the accuracy or veracity of supplied material.




© Technews Publishing (Pty) Ltd | All Rights Reserved