Low-lane-count PCIe Gen 2 switches

26 November 2008 Telecoms, Datacoms, Wireless, IoT

PLX has announced two new ExpressLane PCIe Gen 2 switches with low lane counts: the PEX 8604 (four lanes, four ports) and PEX 8606 (six lanes, six ports). The new additions deliver all the features available in their higher-lane-count siblings, including the exclusive PLX performancePAK and visionPAK suites, non-transparency ports, small package footprints and low power requirements. They are targeted at price-sensitive, mass-production market segments such as set-top boxes, DVRs and multifunction printers.

With 0,8 W typical operation, the switches include features such as non-transparency, configurable port flexibility (x1 or x2), true peer-to-peer fan-out, and two virtual channels per port that help ensure quality of service. All PLX Gen 2 (5 GTps – gigatransfers per second) switches are fully backward-compatible with the PCIe Gen 1 (2,5 GTps) standard.

PerformancePAK capabilities integrated into each switch include PLX’s read pacing (intelligent bandwidth allocation) and dual cast (simultaneously sending data to two ports) features, as well as dynamic buffer allocation (increased throughput by absorbing dynamic increments). Additionally, the chips include PLX’s visionPAK debug diagnostics suite of integrated hardware and software instruments, which consists of a performance monitoring tool, SerDes eye-width measuring, packet generation (for exercising external links at full wire speed) and error injection to evaluate a system’s ability to detect and recover from such errors.

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