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Xilinx releases ISE Design Suite 12
9 June 2010, Design Automation

Xilinx has introduced the ISE Design Suite 12 software that delivers intelligent clock-gating technology to reduce dynamic power consumption by as much as 30%. The new suite also provides advances in timing-driven design preservation, AMBA 4 AXI4-compliant IP support for plug-and-play design, and an intuitive design flow with fourth-generation partial reconfiguration capabilities that lowers system cost for a broad range of high-performance applications.

With full production support for all Virtex-6 and Spartan-6 FPGA families, the new ISE release continues its evolution as a domain-specific design suite with interoperable design flows and tool configurations for logic, digital signal processing (DSP), embedded processing and system-level design. In addition, Xilinx incorporated a number of software infrastructure and methodology enhancements that improve run-time, streamline system integration and expand IP interoperability across its latest generation device families and Targeted Design Platforms.

ISE Design Suite 12 introduces intelligent clock-gating technology with fully automated analysis and fine-grain (logic slice) optimisation capabilities specifically developed to reduce the number of transitions, a primary contributing factor of dynamic power dissipation in digital designs. The technology works by analysing designs using a series of unique algorithms to detect sequential elements (transitions) within each FPGA logic slice that do not change downstream logic and interconnect when toggled. The software generates clock-enable logic that automatically shuts down the unnecessary activity at the logic slice level to accumulate power savings without having to shut off an entire clock network.

Advanced design preservation capabilities in the design suite enable designers to reach design closure fast with repeatable timing results. Designers can partition designs to focus on achieving required timing for critical blocks, and lock those blocks to preserve placement and routing while they work on the rest of the design. To foster plug-and-play FPGA design, Xilinx is standardising IP interfaces on the open ABMA 4 AXI4 interconnect protocol, which eases integration of IP from Xilinx and third party providers and maximises system performance. Xilinx also worked with ARM to define the AXI4, AXI4-Lite and AXI4-Stream specifications for efficient mapping into its FPGA architectures.

Partial reconfiguration technology allows the dynamic modification of FPGA logic blocks by downloading partial bit files without interrupting the operation of the remaining logic. ISE Design Suite 12 makes this technology easy to use with Xilinx FPGAs by providing an intuitive interface and simplified methodology that closely aligns with the standard ISE design flow with which users are familiar. The ISE partial reconfiguration flow now uses the same proven Xilinx tools and techniques for timing closure, design management and floor planning, and design preservation.

Support for fourth generation ‘on-the-fly’ partial reconfiguration technology enables designers to fit sophisticated applications into the smallest possible device. Developers of next-generation wired Optical Transport Network (OTN) solutions can reportedly implement a 40G multiport muxponder interface with one-third fewer resources as compared to devices without partial reconfiguration. Many other applications including software-defined radio also benefit from the increased flexibility provided by on-demand reconfiguration with Xilinx FPGAs.


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