Design Automation


Tool offers advanced untestable-code filtering capability

23 May 2001 Design Automation

Innoveda has announced major extensions to its HDLScore tool for code-coverage analysis. These include untestable-code filtering; support for mixed Verilog/VHDL design environments and variable or signal coverage; and integration with the company's Visual HDL programmable register editor.

HDLScore accurately measures the quality of simulation tests applied to a design through fast, thorough code coverage analysis for the entire design. The tool is used primarily in design verification of semiconductors such as FPGAs, ASICs, and semicustom chips.

"We have used HDLScore as an integral component of our design verification methodology on our last two projects," said Jim Monaco, Design Verification Team Leader at Analog Devices. "HDLScore has proven a valuable asset by helping us measure the quality of our test suite, uncovering potential bugs, identifying uncovered/untested boundary/edge cases, and highlighting non-conformance to RTL style guidelines. Moreover, HDLScore has given us a quantifiable metric to achieve first pass silicon."

HDLScore now offers these enhancements:

* Untestable-code filtering capability. Expressions containing tied or floating signals that create uncoverable entries, skewing results, are removable. This feature gives designers a true coverage picture and also reduces simulation drag.

* Integration into Visual HDL. Coverage statistics are now back-annotated onto Visual HDL's building blocks. This feature enables designers to view graphically from within the Visual HDL GUI what information the functional tests are gathering. Previously, these coverage summary statistics were accessible only externally, in the text-based design environment.

* Support for mixed-Verilog-VHDL design environments. Coverage statistics now can be gathered for designs containing both Verilog and VHDL source. Previously, designs were limited to one language.

* Support for variable or signal coverage. Coverage statistics can now be gathered on individual signals, bits or ranges of signals, and concatenated signals. HDLScore lets designers know if the signal went through all permutations. Designers can determine if a signal achieved all possible states in a functional simulation.

Innoveda is represented in South Africa by ASIC Design Services. For further information contact Kobus van Rooyen, (011) 315 8316, kobus@asic.co.za





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