Pentek’s Model 5352 is a high-speed software radio module designed for processing baseband RF or IF signals from a communications receiver.
It features four 200 MHz 16-bit A/D converters which are supported by a high-performance 32-channel installed DDC (digital down-converter) IP Core, and interfaces ideally matched to the requirements of real-time software radio and radar systems. The board features built-in support for PCI Express (PCIe) Gen. 2 over the 3U VPX backplane.
The front end accepts four full-scale analog RF or IF inputs on front panel SMC connectors at +8 dBm into 50 Ω with transformer coupling into four Texas Instruments ADS5485 200 MHz, 16-bit A/D converters. The digital outputs are delivered into a Xilinx Virtex-5 FPGA for routing, formatting and DDC signal processing.
The Model 5352 SX95T FPGA employs an advanced FPGA-based digital down-converter engine consisting of four identical 8-channel DDC banks. Four independently controllable input multiplexers select one of the four attached A/Ds as the input source for each DDC bank. In this way, many different configurations can be achieved, including one A/D driving all 32 DDC channels and each of the four A/Ds driving its own DDC bank. Each of the DDCs has an independent 32-bit tuning frequency setting ranging from DC up to the A/D sample rate, ƒs.
All of the eight channels within a bank share a common decimation setting that can range from 16 to 8192, programmable in steps of 8. For example, with a sampling rate of 200 MHz, the available output bandwidths range from 19,53 kHz to 10,0 MHz. Each 8-channel bank can have a unique decimation setting supporting up to four different output bandwidths for the board.
The decimating filter for each DDC bank accepts a unique set of user-supplied 18-bit coefficients. The 80% default filters deliver an output bandwidth of 0,8*ƒs/N, where N is the decimation setting. Rejection of adjacent-band components within the 80% bandwidth is better than 100 dB. Each DDC delivers a complex output stream consisting of 24-bit I + 24-bit Q samples at a rate of &402;s/N. Any number of channels can be enabled with each bank, selectable from 0 to 8. Each bank includes an output sample interleaver that delivers a channel-multiplexed stream for all enabled channels within the bank.
The 5352 features 32 power meters that continuously measure the individual average power output of each DDC channel. The time constant of the averaging interval is programmable up to 16 kilosamples. In addition, threshold detectors automatically send an interrupt to the processor if the average power level of any DDC falls below or exceeds a programmable threshold.
Four output MUXs in the SX95T FPGA can be independently switched to deliver either A/D data or DDC data into each of the four output FIFOs. This allows users to view either the wideband A/D data or the narrowband DDC data, depending on the application. Each of the output FIFOs operates at its own input rate and output rate to support different DDC decimation settings between the banks and efficient block transfers to the PCI bus.
The module’s architecture includes a flexible timing and synchronisation circuit for the group of four A/D converters that allows the A/Ds to be clocked by internal or external clock sources and a multiboard timing bus. The timing bus includes a clock, a sync, two gate or trigger signals and a PPS signal. The timing bus can be driven by an internal crystal oscillator, a front panel reference input or the LVPECL bus.
A front panel, 26-pin LVPECL Clock/Sync connector allows multiple boards to be synchronised. In the slave mode, each accepts differential LVPECL inputs that drive the clock, sync, gate and PPS signals for the internal timing bus.
In the master mode, the LVPECL bus can drive the timing signals for synchronising multiple boards. Up to three slave boards can be driven from each LVPECL bus master, supporting synchronous sampling and sync functions across all connected boards. For larger systems, many more boards can be synchronised with an external clock and sync generator.
The 5352 features a unique high-speed switching configuration. A fabric-transparent crossbar switch connects the PCI Express switch with the VPX-P1 connector using Gigabit serial data paths with no latency. This allows the user to select the desired output port on VPX-P1. Programmable signal input equalisation and output pre-emphasis settings on the crossbar switch enable optimisation. The board includes a PCIe Gen. 2 switch which provides a total of 24 PCIe lanes to the fabric-transparent crossbar switch on six ports. Dynamic lane width negotiation within the PCIe switch allows for x1, x4, x8 or x16 widths; these can be selected in any combination.
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