Xilinx has released ISE Design Suite 13.2, providing support for the 28 nm 7-series families including the recently arrived Virtex-7 VX485T device being demonstrated to customers. In addition, this latest edition of ISE Design Suite provides an up to 25% performance increase in designs targeting Virtex-7 2000T devices.
The latest ISE software release also has enhancements to the PlanAhead design and analysis tool, providing partial reconfiguration support for Virtex-7 and Kintex-7 FPGAs, and front-to-back, integrated project management environment for improved productivity in designs targeting Spartan-6 FPGAs, Virtex-6 FPGAs, their defence grade counterparts, and all three 7-series families including initial support for the low-cost Artix-7 family.
ISE Design Suite provides designers the tools they need to facilitate global team design, rapid feedback on key design considerations, best practices for low-power optimisation using the XPower Estimator (XPE) tool, and dynamic power reduction through intelligent clock-gating – all of which is accessible via the PlanAhead tool.
The PlanAhead tool has evolved from an I/O pin planner and floor planner to a comprehensive development environment with integrated front-to-back environment that includes design analysis at each phase of the design cycle – RTL development, IP integration, verification, synthesis, place and route. Enhancements to the tool include new clock domain interaction reports, tooltip language localisation, and Simul-taneous Switching Output (SSO) support for 7-series flip chip BGA (FFG) packages. Updates to the XPE tool enable designers to make power consumption predictions with a high level of accuracy.
In further support of Xilinx’s plug-and-play IP initiative, ISE Design Suite 13.2 enables Advance eXtensible Interface (AXI) interconnect support in CORE Generator system to build higher performance point-to-point architectures. Design teams building their own AXI compliant IP can now run simulations of the AXI interconnect protocol using the optional AXI BFM (bus functional model) verification IP to ensure all interface transactions are working properly. The AXI BFM is now available for ISim as well as Cadence, Mentor and Synopsys simulators.
Users can now also access AXI_PCIe cores from the embedded development kit in designs targeting Virtex-6 and Spartan-6 FPGAs. Additionally, the ChipScope AXIMonitor core in the embedded development kit now supports monitoring of the AXI3 interface and includes an optional AXI protocol checker. The AXI protocol checker is designed around the ARM SystemVerilog assertions and supports 39 Ready/Valid handshake checks.
Partial reconfiguration support for Kintex-7 and Virtex-7 families is now also available in PlanAhead. Partial reconfiguration dynamically modifies logic blocks while the remaining logic operates without interruption. This means designers can use either Virtex-7 or Kintex-7 devices to build flexible systems that are able to swap functions and perform remote updates while operational.
Partial reconfiguration also allows designers to reduce costs and design size by taking advantage of time-multiplexing that ultimately leads to reduced board space and minimises bitstream storage because smaller, or fewer, devices can be utilised. Smaller and fewer devices can also lead to reductions in system power, while swapping out power hungry tasks can minimise the FPGA’s dynamic power consumption.
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