Hittite has introduced the HMC954LC4B 2:1 multiplexer and the HMC955LC4B 1:2 demultiplexer to support up to 32 Gbps data serialisation and deserialisation. The devices are data rate and protocol agnostic, and are aimed at broadband test and measurement, ATE and high-speed DAC and FPGA interfacing applications.
The HMC954LC4B time interleaves two differential input data lanes up to 16 Gbps into a single output data lane up to 32 Gbps. The mux latches the two differential inputs on a rising edge of the input clock and the device uses both rising and falling edges of the half-rate clock to serialise the data.
The HMC955LC4B is designed to deserialise a single input data lane up to 32 Gbps into two separate output data lanes up to 16 Gbps each. It uses both the rising and falling edges of the half-rate input clock, typically 16 GHz, to sample the input data in sequence, and latches the data onto the differential outputs. The device also features a high-speed clock synchronous invert input that allows for data scrambling.
Both the HMC954LC4B and the HMC955LC4B are capable of operating from either a negative or positive 3,3 V supply while exhibiting only 0,2 ps RMS jitter and 3 ps peak-to-peak deterministic jitter. These specifications, combined with low typical power dissipation of 500 mW and low skew between outputs, make them well suited for data aggregation and data source selection in military and communications systems. Fast rise and fall times of 19 ps, programmable output voltage swing capability and DC coupling enable simple interfacing with FPGA devices in ATE applications.
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