Delivering on its commitment to provide customers with an ASIC-like design flow, Actel announced that Synopsys' Design Compiler synthesis tool supports Actel's ProASIC 500K devices. The addition of Design Compiler libraries to the ProASIC design kit enables ASIC designers to work within one of the world's premier ASIC synthesis environments while leveraging the benefits of Actel's nonvolatile, flash-based, 'live-at-power-up,' reprogrammable devices, including shorter and more efficient design cycles.
"Synopsys is the leading provider of ASIC synthesis tools in the world," said Dennis Kish, Vice President of Marketing at Actel. "With these libraries, both Synopsys and Actel customers can now leverage the capabilities provided within Design Compiler and the familiarity of its design environment, while capitalising on the benefits of our nonvolatile, single-chip, reprogrammable ProASIC devices and Designer Series tool flow. This provides designers with the best of both worlds and presents enormous opportunity for our mutual customers."
With ASIC designers considering the advantages of programmable logic for many projects, design flow compatibility is essential. The combination of Synopsys' Design Compiler and Actel's own Designer Series tool suite provides support for rapid timing closure and hierarchical block-based methodologies, similar to the design methodology used by most ASIC designers. To further reduce or eliminate learning costs, ProASIC is also supported by the Module Compiler and DesignWare solutions from Synopsys.
Actel's Designer Series tool suite was designed to support both ASIC and FPGA design flows. The toolset is based on a complex, multimillion gate-capable ASIC layout tool that includes timing-driven as well as incremental place and route capabilities. The software integrates a global router, static timing analyser and an engineering change order (ECO) editor into an advanced design flow. Additional capabilities and benefits include automated memory generation, floor-planning, power estimation, a layout viewer for identifying and optimising critical paths and standard formats for creating custom wireload models for future synthesis passes.
The ProASIC 500K family consists of four devices ranging in size from 98 000 to 473 000 system gates and includes up to 65 Kb of embedded two-port memory. The clocking architecture allows the use of up to 56 low-skew clock spines for external or internal clock signals. It combines the advantages of ASICs with the benefits of programmable devices through its nonvolatile flash technology.
Actel's Designer Series software is available on a 45-day free evaluation licence. Design Compiler is available directly from Synopsys.
For further information see www.actel.com, www.synopsys.com, or contact Kobus van Rooyen of local representative, ASIC Design Services, (011) 315 8316, [email protected]
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