Agilent Technologies recently demonstrated a 32 Gbps bit error ratio tester (BERT) at the ECOC exhibition in Amsterdam.
The N4960A modular BERT is suitable for product design, device characterisation and production test of devices and systems operating up to 32 Gbps. It is available in 17 Gbps and 32 Gbps configurations and is aimed at 100G Ethernet, CEI 28G VSR and 32G Fibre Channel applications.
The pattern generator and error detector, which operate at full rate speed without external multiplexers or demultiplexers, are configured as small, remotely mountable heads. They attach to the half rack-wide BERT controller with one-metre cables, which pass clock signals, control communications and power to the heads.
The pattern generator output and error detector input are generated and processed directly in the heads, close to the connectors. This configuration minimises cable lengths and associated signal degradation between the heads and the device under test.
The pattern generator provides hardware-generated PRBS patterns, as well as user-defined patterns up to 8 Mb long. A library of common telecom and datacom stress patterns is included and a powerful pattern editing tool simplifies the process of generating and modifying user patterns.
Users control the system with Signal Integrity Studio software, which is included with the instrument. The software provides an intuitive setup and control interface to simplify operation.
100G Ethernet applications that require four lanes of 25,78 or 28+ Gbps data are addressed with four single-channel systems. The four-channel configuration can be configured to operate with a single synchronous clock or four asynchronous clocks. This provides an advantage over other four-channel BERTs that operate only with synchronous clocks, which makes it impossible to verify communication ASICs such as gearbox chips with independent clocks – a requirement in some standards.
The modular configuration allows users starting their initial 100G designs to purchase a single-channel BERT to bring up the basic 28G link design. Once the basic link is stable, the user can purchase the remaining three channels needed for 100G operation, thereby minimising upfront capital expenditures. For devices with built-in error detection and counting capability, the N4960A can be configured with pattern generation only.
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