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Direct digital synthesizer enables superior recovered timing signal
27 March 2002, Telecoms, Datacoms, Wireless, IoT
In optical communications systems, there is frequently a need for recovering a timing signal from a data stream. The recovered timing signal often displays unacceptable jitter and noise characteristics. It is desirable to clean up a 'dirty' timing signal to obtain one that is jitter- and noise-free.
A common solution for cleaning up a jittery timing signal is a PLL (phase lock loop) with a suitably designed analog loop filter. This analog loop filter design must be optimised for a relatively narrow set of operating conditions. Also, this filter may be highly dependent upon the accuracy of several component values in order to achieve acceptable performance. This can make such a filter expensive and the resulting solution inflexible.
Analog Devices says that much better results can be obtained through the application of its AD9852 DDS (Direct Digital Synthesizer) in a digitally controlled oscillator (DCO) configuration. This design uses a digital processor (such as a microprocessor or DSP) to implement the PLL loop filter in software. This digital loop filter can be complex to achieve any desired transfer function, and can also be adaptable or reconfigurable for changing circumstances.
The DCO shown in the diagram takes advantage of the ultra-fine tuning resolution of the AD9852 DDS. This 300 MSa/s DDS features a 48-bit frequency tuning word that achieves 1 milli-Hz or better resolution in frequency settability. The AD9852 also features a parallel interface port that allows the controller to update its tuning value very quickly.
The combination of microhertz digital tunability and the digitally implemented PLL loop filter leads to a superior recovered timing signal and unmatched flexibility of design, according to the company. |
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