Historically, designing PCI bus products has been an extremely difficult proposition...
Most current FPGA PCI solutions continue to be of limited value because they are gate-level netlists or pre-placed designs, both of which place significant constraints on the designer and the design tools. As a result, it is difficult to consistently meet timing once the core is integrated with additional functionality.
However, Actel's antifuse-based SX-A, SX and MX FPGA families provide the performance and routing resources that allow the use of a highly flexible RTL core while still hitting the stringent PCI performance requirements.
The only soft RTL core in the FPGA market offering customers full portability to ASICs, new CorePCI flexibility combined with Actel antifuse silicon greatly simplifies high-speed designs.
Actel's Version 5.11 release of its CorePCI with master functionality adds extensive design flexibility benefits for PCI bus design. A unique benefit of Actel's PCI core is the use of a soft RTL (register transfer level) design flow that provides complete PCI design portability to ASICs. This soft core, when combined with Actel silicon, provides a low-power, high-performance, cost-effective and very flexible platform for a broad scope of PC and embedded PCI needs in communications, consumer, computer industrial and military applications.
"Vista Controls has used Actel's PCI solution in six designs since 1996. We like the ease and flexibility of integrating our backend designs to the Actel PCI core and are impressed with the routability and speed of Actel's SX FPGAs," said Terry Harkul, EE Manager, Vista Controls Corporation. "The ease of integration is possible because of Actel's flexible backend scheme of de- multiplexed control signals combined with zero-wait-state operation."
The enhanced version of CorePCI is available as customisable VHDL and Verilog-HDL code which (unlike other handcrafted firmware or hard formats) offers flexibility in design and portability to ASICs.
Finally, the core includes SDRAM, DRAM and FIFO controllers to ensure that designers can create the optimum memory interface for designs that require it.
"Actel uniquely creates a simple design transfer path to volume production ASIC devices," said Anil Reddy, Senior Manager of IP and Design Services Marketing at Actel. "We believe an RTL implementation such as ours, in contrast to hard-wired silicon or structural netlist approaches, moves high-speed PCI design from the position of 'real PCI' to 'really easy PCI'."
The CorePCI 5.11 macro conforms to the PCI local bus specification 2.2 and includes target, target+DMA and master functionality. It provides 32/64 bit bus widths and 33/66 MHz performance using the 54SX device family from Actel.
Actel's CorePCI macro is pre-verified in Actel silicon and the core was successfully tested for performance in multiple PCI platforms at compliance workshops. Functionality of the new PCI core macro was also proven in customer designs. In addition, the core was validated to work in Synopsys, Exemplar and Synplicity synthesis-based design flows.
For further information contact Kobus van Rooyen, ASIC Design Services, (011) 315 8316 or [email protected]
| Tel: | +27 11 315 8316 |
| Email: | [email protected] |
| www: | www.asic.co.za |
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