Integrated design environment eases FPGA development - 14 August 2002 - ASIC Design Services

Integrated design environment eases FPGA development
14 August 2002, Design Automation

Actel has announced the availability of version 2.2 of its Actel Libero integrated design environment for FPGA development and design. Using the Libero 2.2 design environment, designers will be able to leverage enhanced tools for synthesis and test bench generation from Synplicity and SynaptiCAD, respectively. Actel says its own place-and-route and verification tools have also been updated. These enhancements will offer designers greater ease of use, streamlined product design cycles and decreased time-to-market when designing next-generation FPGA solutions, says Actel.

"With new versions of industry-leading tools from Actel, SynaptiCAD and Synplicity, Libero tool suite makes it easier for designers to quickly reach their aggressive performance and logic utilisation goals," said Saloni Howard-Sarin, tools marketing director at Actel. "With this announcement, Actel continues its commitment to provide quality support for Actel's FPGA families and to deliver a complete design environment that yields substantial time-to-market advantages for our customers."

Enhancements

Libero 2.2 tool suite uses the fast, incremental timing analysis engine and automated register re-timing feature of the Synplicity Synplify software. This makes timing estimations even more accurate and produces highly optimised circuits with fewer design iterations. With automatic re-timing, Synplify software eliminates the labour-intensive process of analysing critical paths and changing HDL code to balance delay and can automatically reposition registers within combinatorial logic to balance routing and ultimately improve circuit performance.

For test bench generation and management, Libero 2.2 design environment integrates SynaptiCAD's WaveFormer Lite version 8.3, a graphical entry tool that allows the user to describe the stimulus for the simulation graphically and then convert the graphical information into a VHDL or Verilog test bench.

Also included is Actel's enhanced Actel Designer R1-2002 software solution that contains new user-friendly productivity tools to accelerate and automate the system design process without forcing the designer to relinquish control. Designer software now also delivers robust power analysis, allows hierarchical netlist viewing and provides support for fixed pins. Actel's Silicon Explorer II software, a verification and logic analysis tool for realtime, in-system internal device probing, has been upgraded to deliver test and debug support for additional Actel FPGA devices.

The Libero Silver and Evaluation versions may be used by designers for one year and 45 days, respectively, free of charge.

For more information: ASIC Design Services, 011 315 8316, kobus@asic.co.za