Actel and First Silicon Solutions (FS2) are offering the configurable logic analyser module (CLAM) System for realtime logic analysis of designs using Actel's flash-based ProASIC and ProASICPLUS field-programmable gate arrays. In addition to the traditional internal on-chip option, FS2's CLAM System also offers unique off-chip trace and triggering support, which allows users to reduce the time required to debug and optimise the system while minimising the use of system gate resources and available device pins. Embedded in the Actel device, the CLAM System enables users to more easily test and debug their flash-based logic designs for ASIC alternative applications in the industrial, communications, networking and avionics markets.
The CLAM System consists of FS2's on-chip instrumentation (OCI) intellectual property, a hardware probe for communications with the FPGA target, and Windows-based control and display software. The intellectual property is configurable with trigger and trace resources, offering a large number of options, including configuration for either on-chip or off-chip trace and triggering. The solution allows the user to select up to 128 internal nodes for analysis at compile time. During run-time, the user is able to view trace and specify trigger conditions on up to 32 channels, or nodes. The CLAM System software makes it easy to set up and configure trace and trigger conditions and view the trace display of the output logic waveforms.
For more information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, kobus@asic.co.za
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