Synplicity has further extended the timing-driven performance advantage of its FPGA synthesis software. With the company's unique true timing-driven approach to synthesis, the latest release of its Synplify Pro software offers users the ability to more easily optimise for area after their speed goal is met, potentially reducing device size and saving money in device costs. Synplicity says that additional optimisations have also been added to the software to further its performance quality of results (QoR), including the addition of register re-timing for Actel ProASIC and ProASIC Plus FPGAs as well as increased performance benefits for Altera Stratix devices and Xilinx Virtex-II Pro devices.
This latest Synplify Pro 7.3 software release also features automatic gated clock conversion, eliminating the time-consuming task of translating ASIC-based gated-clock elements into FPGA-based clock-enable structures. Additionally, it also offers added support for Xilinx COREgen software and Altera clear box models, providing better timing estimation for IP blocks.
"We believe the performance benefits users can experience with this latest version of the Synplify Pro software will far exceed those of competing products," said Jeff Garrison, director of marketing for FPGA products at Synplicity. "Today's design managers are constantly looking for ways to cut design costs, and with our true timing-driven approach to synthesis, we believe users will be able to obtain significant area reduction in their devices, potentially saving tens or hundreds of thousands of dollars in device costs. Also, with the addition of automatic gated clock conversion, we have made it much easier for ASIC designers to efficiently and quickly target FPGAs without major HDL code changes."
Most FPGA synthesis tools optimise for area or performance, but do not provide the ability to optimise for area once the speed goal is met at a global level. However, using the Synplify Pro software, designers are able to specify a timing frequency on their clocks, and once that frequency is met, the software automatically optimises for less area, while continuing to meet the user's performance targets. Synplicity believes this approach to synthesis enables optimal area reduction resulting in lower device costs.
The software now also features automated register re-timing support for Actel's ProASIC and ProASIC Plus device families. With re-timing, registers are automatically moved within combinatorial logic of the design to improve circuit performance. Here Actel device users can expect to experience an average of more than 15% performance improvements compared to previous releases without re-timing. It also supports Xilinx and Altera devices.
The automatic gated clock conversion feature included within this software release, enables users to efficiently migrate an existing ASIC design into an FPGA. With this feature, ASIC designs that have been written using gated clocks are automatically translated to clock enable structures in the target FPGA, significantly reducing the need for manual changes to the HDL code. This automated feature can save days in the design process that would have been required to convert an average-sized ASIC into an FPGA, says Synplicity.
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