STMicroelectronics has developed an embeddable digital signal processor (DSP) core that can be implemented in versions that run at above 600 MHz or that consume less than 0,1 mW/MMAC (Million MAC) in a typical portable telecom application. Based on ST's ST100 DSP architecture that allows user-customised instruction sets, the company's ST122 Dual MAC core is supported by an evaluation chip and a complete development platform.
Available in the form of synthesizable IP, the ST122-DSP can be mapped into various versions ranging from ultra-low power to high-speed operation. This flexibility makes it suitable for a broad spectrum of applications including new generation mobile terminals, cellular infrastructure equipment, networking, broadband modems, voice-over-IP, data storage and mobile multimedia.
Like all ST100 architecture-based cores, the ST122 combines VLIW and RISC features to achieve the best balance between performance and code size. Flexible instruction modes allow a mixture of 16, 32 and 128-bit instructions and instruction sets can be customised to add applications-specific operators. Custom extensions have demonstrated an important performance boost in ADSL, GPRS/EDGE, audio and video algorithms while adding minimal silicon overhead. Custom instructions are controlled through the ST100's tightly coupled co-processor extension interface and are fully supported by the ST100 DSP toolchain.
To support the demanding performance needs the dual-MAC ST122 core can fetch four 32-bit instructions using 128-bit instruction mode and execute them in a single clock cycle. Highly efficient memory interfaces allow the connection of a large amount of flat data memory. The ST122 evaluation device includes 16 KB of L1 Program cache, 256 KB of L2-Program memory and 2x64 KB of data memory accessed at the DSP core's maximum clock speed.
Designed for easy and optimal integration into complex system-on-chip products, the ST122 is supported by a full range of peripherals.
For more information contact Simon Churches, Arrow Altech Distribution, 011 923 9600, [email protected]
Ultra-low power MEMS accelerometer Altron Arrow
Analogue, Mixed Signal, LSI
Analog Devices’ ADXL366 is an ultra-low power, 3-axis MEMS accelerometer that consumes only 0,96 µA at a 100 Hz output data rate and 191 nA when in motion-triggered wake-up mode.
Read more...ESP32-C6 achieves PSA-L2 iCorp Technologies
DSP, Micros & Memory
Espressif Systems recently announced that its ESP32-C6 microcontroller has achieved PSA Certified Level 2 (PSA-L2) security certification, making it the first RISC-V-based MCU to reach this level.
Read more...Microprocessor with integrated NPU Avnet Silica
DSP, Micros & Memory
The RZ/G3E from Renesas is a microprocessor integrated with quad CPU and NPU in one chip, improving power efficiency, reliability, and security.
Read more...Dual-core support in NECTO Studio
DSP, Micros & Memory
MIKROE recently announced that version 7.3.0 of its NECTO Studio Integrated Development Environment now supports dual-core MCUs, allowing designers to program and debug each core independently.
Read more...Post Quantum Cryptographic firmware library
DSP, Micros & Memory
The STM32 post-quantum cryptographic library enables developers to satisfy application requirements for any combination of data integrity, confidentiality, identification/authentication, and nonrepudiation.
Read more...Converting high voltages without a transformer Altron Arrow
Editor's Choice Power Electronics / Power Management
With appropriate power converter ICs, such as the LTC7897 from Analog Devices, many applications can be suitably powered without having to use complex and cost-intensive transformers.
Read more...MultiVolt series of oscillators Future Electronics
DSP, Micros & Memory
The ECS-3225MVQ from ECS Inc. is a compact, quartz-based MultiVolt oscillator designed for precision timing in automotive, industrial, and portable electronic systems.
Read more...Drive innovation with AURIX TriCore MCUs Future Electronics
DSP, Micros & Memory
Infineon’s AURIX TriCore family balances safety, performance, and energy efficiency to offer a scalable and future-ready portfolio.
While every effort has been made to ensure the accuracy of the information contained herein, the publisher and its agents cannot be held responsible for any errors contained, or any loss incurred as a result. Articles published do not necessarily reflect the views of the publishers. The editor reserves the right to alter or cut copy. Articles submitted are deemed to have been cleared for publication. Advertisements and company contact details are published as provided by the advertiser. Technews Publishing (Pty) Ltd cannot be held responsible for the accuracy or veracity of supplied material.
printer friendly version