With design cycle times decreasing, and the need to deliver 'right the first time' designs, PCB designers are constantly on the look-out for tools to help save them time and help deliver a quality end product. The ability to implement design re-use helps meet both of these goals.
Design re-use is common in many industries. A trip to the local car dealer will show the same radio/CD player, as well as the same engine, used in several car models. Design re-use at the IC level has saved millions of dollars. The time and money involved to create, design, and test the original portion of the design to be re-used need only be invested once. More importantly, the integrity of the circuit is saved and the intelligence is preserved. More organisations are looking at design re-use at the system level, on and between PCBs, to help them meet time to market goals while increasing the quality and reliability of products.
There are several forms of design re-use. A generic definition of design re-use is the ability to select a section of a design, save it as a unique entity or element, and then pull it into a new design database or replicate it in an existing design. The physical integrity and logical intelligence of the circuit is always maintained. True design re-use must resolve conflicts in the design over duplicate reference designators, how net names are managed, and other design data differences.
Forms of design re-use
Physical design re-use (PDR), allows more EDA users to take advantage of the benefits provided by this methodology. PDR focuses on saving physical data on the printed circuit to be used on a future design or replicated in an existing one. The data to be saved includes placement, routing, via structures, design rules, layer stack up, and more. The user must be able to store this data in a library as a standalone element which can then be accessed for a future design. By saving this element to a library, it will be protected from inadvertent modifications. Whether the re-use element is added to a new design or replicated, the process must consider and reconcile reference designator assignments and determine how to add new nets to the design, or merge the net with existing nets.
Logical design re-use (LDR) is another form of design re-use. Most schematic capture systems have a methodology for re-using sections of circuitry. This may involve simply saving the appropriate pages of the schematic as a separate design to be used later, or defining the desired page(s) as a hierarchical block to be re-used. The data that makes up a schematic is minimal, consisting of a graphical symbol and attributes describing the part and nets. It is relatively easy to save this data for re-use or duplication.
A third type of design re-use is the combination of logical and physical design re-use. In this case, a relationship is created between a section of the schematic and the corresponding section of circuitry on the PCB. This whole entity is then stored to a library for future use.
Physical design re-use addresses several challenges facing design engineers and PCB designers. A design may include multiple channels which must be replicated with identical placement and routing. Without automated tools to accomplish this, it is a very tedious, error-prone, and time-consuming process. Because of the time to market pressures, designers need to have the ability to re-use proven sections of previous designs, or 'golden circuits'. The efficiency of re-using a proven circuit is realised not only in the design space, but also during other phases of the development cycle. For example, a power supply on a previous design has been tuned to work to specification, and also tuned to meet EMC guidelines. Going to test with a high degree of confidence will allow designers to meet schedules.
Similar to golden circuits, many designs within an organisation will use the same chipsets (ie, graphic chips, microprocessors, DSPs) within a product family, placed with the same ancillary components and routed identically. Or, they may use the same BGA package and want to maintain the same via fanout pattern and bypass capacitor placement. This is referred to as 'circuit replication'.
The need for design re-use is universal throughout the electronics industry. Whether you are a telecoms company whose products often involve multiple channels; a graphics card company using a special chipset and supporting devices; or a multinational supplier of power supply modules that need to meet regulatory requirements on different continents, design re-use technology can be used to reduce product development design cycles and ensure the consistent physical integrity of your products.
Another approach to PDR
To date, the EDA industry has largely ignored the issue of PDR. Logical design re-use is available in some form from most schematic capture systems. But this excludes a large part of the problem that needs to be solved - the physical. A few vendors offer logical/physical re-use in specific configurations. These are tied to the vendors schematic capture system along with their PCB layout tool. In some cases, an additional library management tool may be required. Until now, there have been only limited provisions for physical design re-use in the PCB layout tool alone, with no tie to the schematic environment.
However, there is finally another approach to physical design re-use available, focused on preserving the physical integrity of the circuit.
A different approach is needed for printed circuit designers, one where all physical structures are maintained (placement, layer stack up, via structures, routing, physical design rules), as well as connectivity. This new approach should not be referential. The user should not need to rely on naming conventions (reference designators and net names) to maintain the physical interconnect structure of a circuit. The solution should also be unique in that it be independent of the schematic capture system.
As an illustrative example, let us say a telecommunications company which uses on-board modems wishes to re-use the modem section on a new design. With the schematic complete, including the proven (logic) circuitry, the net list is read into the PCB layout system. The designer then opens and applies the modem, or golden circuit, saved from the previous design. There are several issues that must be addressed during this process. One, since the complete parts list has been brought into the PCB layout tool, the process must automatically choose from the components currently in the database to build the golden circuit. This process must not consider reference designators as the re-use element may have been created when one of the ICs in the design was U1. In the new design, if U1 already exists on another device, there will be a major conflict. Likewise, net names must not be considered, but connectivity looked at instead. If in the original re-use the power net is called Vcc, but in the new design the engineer calls it Vss, a conflict again exists. If components are added to the database to build this new golden circuit in the new design, synchronisation with the schematic is immediately lost. Using the components already in the database maintains the relationship with the schematic and helps ensure correct by construction design. Since the golden circuit contains routing, it is important that this data be brought in correctly, independent of what the design rules, via padstacks, and design rules are set for in the new design. The integrity of this proven golden circuit must be maintained at all times.
The requirements of PDR in the same design are challenging. In the case of a multichannel design, one channel would be placed and routed. As a second channel is instantiated, it is important that the model of the first instantiated section to be used, and that the existing components in the design be used, to create the second re-use. Again, the link to the schematic is maintained. This saves many hours of manual, error-prone effort to resynchronise the schematic with the physical layout. This new approach requires that reference designators or actual net names not be considered, but rather, the connectivity and other attributes.
The process that facilitates this approach is based on the subgraph isomorphism algorithm, and is referred to as the isomorphic process, or intelligent element builder. Using an existing re-use element as a model, when a re-use element is being built, this process looks at all parts that are available in the design to determine which components are to become re-use members. It goes through extensive checking and reconciliation routines, looking at part names (but not reference designators), footprint names, pin numbers, connectivity (but not net names), and other attributes to determine and build matching patterns based on the original re-use element. When a power supply is brought in from the re-use library into the new design, components are not added to the design, but matches are found for identical components in the database. This process, based on using a model that is independent of specific identifiers, is what makes this new approach to design re-use a schematic-independent solution. Since no ties to the schematic are required, users are free to choose the schematic environment that is best for their organisation, yet still reap the benefits of physical design reuse.
Summary
EDA tool users require the ability to re-use proven, tested circuits in new designs and quickly and consistently replicate channels. They will no longer accept the restriction that a specific design environment (schematic capture and PCB layout) must be used. On the contrary, they want the freedom to choose the best in class tool at each phase of the design cycle, yet are unwilling to accept the application limitations due to the mixed tool environment. This approach - physical design re-use - enables users to take advantage of the benefits of design re-use independent of the schematic capture tool. These benefits include shorter development cycles and higher quality products. Through the isomorphic process, re-use elements can be built from components from the schematic environment to an existing PCB database, always keeping the PCB layout database synchronised with the schematic.
For more information contact Kobus van Rooyen, ASIC Design Services, 011 315 8316, [email protected]
| Tel: | +27 11 315 8316 |
| Email: | [email protected] |
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